Thanks Omar,
By the way, Does the DPLL in the SPDIF Rx always output 128x the sampling freaquency clock?(e.g. 5,644,800 Hz at 44.1 kHz, and 12,288,000 Hz at 96 kHz)
I want a constant output clock from I2S.
Is there a way to output a constant clock (preferably 45158400Hz or 49152000khz) from I2S, regardless of the SPDIF sampling rate?