i.MX 93 Using External Clock for Fractional PLL 'VIDEO_PLL'

[dunk]

Hi Community,

According to section 70.5 'PLL' in document 'IMX93RM.pdf', fractional PLL, including SYSTEM_PLL1, DRAM PLL, AUDIO_PLL and VIDEO_PLL.
I would like to feed my own clock (via CLKIN1 or CLKIN2) to VIDEO_PLL which will be used as clock root 'enet_timer2_clk_root'.

How do I do for this usage? Couple setting from RM as below:

- Register 'CLOCK_ROOT88_CONTROL': set to 11: VIDEO_PLL_CLK
- What's the register to select 'CLKIN1' or 'CLKIN2' for VIDEO_PLL_CLK? Register 'GPR20' seems to be relevant, but not precisely stated.

GPR20 (SRC General Purpose Register 20):
anamix_atx_sense_bus_enable_lv = gpr_src_general_reg_gpr20_gpr[0] default 0
anamix_pll_clk_mux = gpr_src_general_reg_gpr20_gpr[4:1] default 0
anamix_clkin_mux = gpr_src_general_reg_gpr20_gpr[6:5] default 0
anamix_clkin_mux2 = gpr_src_general_reg_gpr20_gpr[8:7] default 0
anamix_clkin1_ipp_ibe = gpr_src_general_reg_gpr20_gpr[9] default 1
anamix_clkin2_ipp_ibe = gpr_src_general_reg_gpr20_gpr[10] default 1

[joanxie]

what peripheral do you need to use  CLKIN1 or CLKIN2? do you use any OS？pls share more detailed information with me

[dunk]

Hi Joan,
The idea is to use external clock for driving the 1588 of ENET1 without sharing the same clock of rest of system.
With eternel clock, we can use additional DPLL for beter timing control.

[joanxie]

CLKIN1/CLKIN2 is for test purpose, if you need set the frequency for enet_timer2_clk_root, you just need to choose the source from ROOT88 you already know it, then set the corresponding pll frequency, you can refer to the dts file

linux-imx/arch/arm64/boot/dts/freescale/imx93.dtsi at lf-6.6.y · nxp-imx/linux-imx

clocks = <&clk IMX93_CLK_ENET1_GATE>,
<&clk IMX93_CLK_ENET1_GATE>,
<&clk IMX93_CLK_ENET_TIMER1>,
<&clk IMX93_CLK_ENET_REF>,
<&clk IMX93_CLK_ENET_REF_PHY>;
clock-names = "ipg", "ahb", "ptp",
"enet_clk_ref", "enet_out";
assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>,
<&clk IMX93_CLK_ENET_REF>,
<&clk IMX93_CLK_ENET_REF_PHY>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
<&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>,
<&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
assigned-clock-rates = <100000000>, <250000000>, <50000000>;

[dunk]

Thanks for this details and dts example. I'll try this.