i.MX 8X LPSPI sample point

[EAlepins]

In i.MX8 QXP Reference Manual Rev.0 (05/2020), chapter 16.12 "Low Power Serial Peripheral Interface (LPSPI)" of the Audio DMA Subsystem, the CFGR1[SAMPLE] register bit is described and says that it is possible for the i.MX to sample the MOSI later than on first SCLK edge. However, there is no details about how much later this is. I was expecting the datasheet to give details and timing diagram relative to this, but it is not the case. I am using datasheet IMX8QXPAEC Rev. 4 (01/2022).

Note that the Reference Manual says "The delayed version of the LPSPI_SCK is delayed by the LPSPI_SCK pin output delay, plus the LPSPI_SCK pin input delay". However, the datasheet does not say what are the values of the "LPSPI_SCK pin output delay" and "LPSPI_SCK pin input delay"...

Please help. I've configured the SPI as TCR.CPOL=0b0 and TCD.CPHA=0b1 (i.e. data driven on rising edge, sampled on falling edge). My timing analysis does not work and I need the i.MX to sample MOSI later than the rising edge.

Thanks,

Etienne

[EAlepins]

Hi,

Thanks for your reply. So, with a 40 MHz master SPI, it means that with CFGR1[SAMPLE]=1, SDI setup time is no longer 5 ns but 2 ns, right? And that the SDI hold time is unchanged? (i.e. 4 ns) I would have expected the hold time to be increased since the sample point is shifted right in time...

->The input data setup time in master mode with delayed LPSPI_SCK edge is equal to the input data setup time in slave mode.

The information you gave me is not found in the documentation. Could you raise a documentation clarification ticket on that please?

Thanks,

Etienne

[Sanket_Parekh]

Hi @EAlepins 

I hope you are doing well.

In the datasheet, Only minimum values are specified for setup and hold time.

"The input data setup time in master mode with delayed LPSPI_SCK edge is equal to the input data setup time in slave mode"

above information is given at CFGR1[SAMPLE] bit of 16.12.3.1.9 Configuration Register 1 (CFGR1) in i.MX 8DualX/8DualXPlus/8QuadXPlus Applications Processor Reference Manual.

Thanks & Regards,

Sanket Parekh

[EAlepins]

Hi,

Thanks. I hadn't seen it. However, shouldn't that impact the hold time as well? For example, if CFGR1[SAMPLE] reduces the setup time by 3 ns, shouldn't it increase the hold time by 3 ns also?

Étienne

[Sanket_Parekh · Accepted solution]

Hi @EAlepins 

I hope you are doing well.

shouldn't that impact the hold time as well? For example, if CFGR1[SAMPLE] reduces the setup time by 3 ns, shouldn't it increase the hold time by 3 ns also?

[Ans]: Yes, It will increase hold time as well.

          in, Datasheet LPSPI timings—Slave mode in the datasheet is correct. 

          as stated earlier " The input data setup time in master mode with delayed LPSPI_SCK edge is equal to the input data setup time in slave mode."

          Information for hold time is not specified, but it will increase.

Thanks & Regards,

Sanket Parekh

[Sanket_Parekh]

Hello @EAlepins ,

I hope you are doing well.

Q) [Community] i.MX 8X LPSPI sample point

->When pin 1(SAMPLE) is set in Configuration Register 1 (CFGR1), the LPSPI master will sample the input data on a delayed LPSPI_SCK edge, which improves the setup time when sampling data.

->The input data setup time in master mode with delayed LPSPI_SCK edge is equal to the input data setup time in slave mode.

->Please refer to the below section in the datasheet for input data setup time in slave mode.
LPSPI timings—Slave mode in datasheet
https://www.nxp.com/webapp/sps/download/preDownload.jsp?render=true

Thanks & Regards,

Sanket Parekh