Hi,
There is a 4GB DDR4 on my board, then I do the DDR stress test, region 2 is failed, it could not go to t0.2. However, it is ok if I set the device information as same as the MEK board, which means it is ok when I tested as 3GB DDR4. Could someone give me some advices please? Thanks.
The log is:
*************************************************************************
MX8 DDR Stress Test Version: ER14
Built on Mar 27 2020 12:28:23
*************************************************************************
--Set up the MMU and enable I and D cache--
- This is the Cortex-A35 core
- Check if I cache is enabled
- Enabling I cache since it was disabled
- Push base address of TTB to TTBR0_EL3
- Config TCR_EL3
- Config MAIR_EL3
- Enable MMU
- Data Cache has been enabled
- Check system memory register, only for debug
- VMCR Check:
- ttbr0_el3: 0x13d000
- tcr_el3: 0x2051c
- mair_el3: 0x774400
- sctlr_el3: 0xc01815
- id_aa64mmfr0_el1: 0x101122
- MMU and cache setup complete
*************************************************************************
ARM Clock(CA35): 1200MHz
DDR Clock: 1200MHz
============================================
DDR configuration
DDR type is LPDDR4
Data width: 32, bank num: 8
Row size: 16, col size: 10
Two chip selects are used
Number of DDR controllers used on the SoC: 1
Density per chip select: 2048MB
Density per controller is: 4096MB
Total density detected on the board is: 4096MB
Command Bus Training was executed
No DDR data training errors detected for DDRC0
============================================
MX8QXP: Cortex-A35 is found
*************************************************************************
DDR Stress Test Iteration 1
--------------------------------
--Running DDR test on region 1--
--------------------------------
t0.1: data is addr test
....
t0.2: row hop read test
...
t1: memcpy SSN armv8_x32 test
....
t2: byte-wise SSN armv8_x32 test
..
t3: memcpy pseudo random pattern test
....................................................................
t4: IRAM_to_DDRv1 test
...
t5: IRAM_to_DDRv2 test
--------------------------------
--Running DDR test on region2--
--------------------------------
t0.1: data is addr test
...
