i.MX 8M Mini output MCLK select

[jonathan_miles]

The iMX8M reference manual shows the following input/output options for the SAIn MCLK pad:

jonathan_miles_1-1733781991181.png

What register controls the right hand mux for the output signal - between SAIn_MCLK_OUT and SAIn_CLK_ROOT?

Is it the corresponding GPR_SIAn_SEL1 bit in IOMUXC_GPR_GPRn register?

jonathan_miles_2-1733782285847.png

If so, when MCLK is an output where does the SAIn_MCLK signal come from? How is it different from SAIn_CLK_ROOT?

[joanxie]

1) yes,  GPR_SIAn_SEL1 bit can choose it

2)when MCLK is an output where does the SAIn_MCLK signal come from? How is it different from SAIn_CLK_ROOT?

>refer to the RM, if MCLK is an output, can come from SAIn_CLK_ROOT or MCLK_OUT, Note that the SAI IP MCLK out, MCLK_OUT is always derived from the ipg_clk_sai_mclk (MCLK[1]) input, you can choose it from IOMUXC_GPR_GPR6

[jonathan_miles]

Hi joanixie, thanks for your reply.

Referring to the reference manual, if ipg_clk_sai_mclk(MCLK[1]) is the source for MCLK_OUT, then Figure 13-2 indicates that the source of ipg_clk_sai_mclk is SAIn_CLK_ROOT or SAIn_MCLK:

jonathan_miles_0-1733813799736.png

Which leads us back to the original question: what's the source of SAIn_MCLK in this configuration?

Thanks,

Jonathan

[joanxie]

as I replied before, SAIn_Mclk is from SAIn_CLK_ROOT which is from CCM and another source is from SAIn.MCLK, you can choose it from bit5 of IOMUXC_GPR_GPR6

joanxie_0-1733972749066.png