i.MX8M mini SAI MCLK output divider

[jonathan_miles]

I would like to use the post-divider on the audio master clock to produce a slower clock on the SAIn_MCLK pin.

I've tried setting MOE, DIVEN and DIV in the SAI MCLK Control Register but haven't seen any difference in the resulting MCLK output signal on the pin.

I've also tried changing GPR_SAIn_MCLK_OUT_SEL in the IOMUX_GPR_GPRn register but not seen any difference.

What other bit of configuration am I missing?

[joanxie]

what OS do you use? what clock source do you choose for the SAIn_MCLK pin？ maybe you can refer to the link as below, if you use linux, you can set the clock in the dts directly, if you don't use any OS, need to confirm what clock source as your SAIn_MCLK, from any io pad or from ccm

Solved: iMX8M Mini: How to use MCLK pad as master clock input? - NXP Community

[jonathan_miles]

Hi joanxie,

The configuration I'm after is when SAIn_MCLK is an output pin. We're using Linux and the SAIn_MCLK is derived from the SAIn_CLK_ROOT (and then from the audio PLL).

What I would like to do is use the post-clock divider in the MCLK control register (MCR: 0x300n0100) to divide down the output SAI_MCLK after it is used by the SAI.

The only code in the kernel I can find that writes to MCR controls the output enable (MOE). There isn't any example of setting up the divider that I can see.

Thanks,

Jonathan

[joanxie]

The configuration I'm after is when SAIn_MCLK is an output pin. We're using Linux and the SAIn_MCLK is derived from the SAIn_CLK_ROOT (and then from the audio PLL).

>yes correct, you can choose this from SAIn_CLK_ROOT

The only code in the kernel I can find that writes to MCR controls the output enable (MOE). There isn't any example of setting up the divider that I can see.

> I didn't find such example for this, you need add this in the sai driver,

linux-imx/sound/soc/fsl/fsl_sai.h at e0f9e2afd4cff3f02d71891244b4aa5899dfc786 · nxp-imx/linux-imx

I refer to the header file, you need enable FSL_SAI_MCTL_DIV_EN BIT first, if you just want to test, you can use memtool to set the register, if you need add to the driver, you can refer to the MOE settings, then add by yourself for other bits

/* SAI MCLK Control Register */
#define FSL_SAI_MCTL_MCLK_EN BIT(30) /* MCLK Enable */
#define FSL_SAI_MCTL_MSEL_MASK (0x3 << 24)
#define FSL_SAI_MCTL_MSEL(ID) ((ID) << 24)
#define FSL_SAI_MCTL_MSEL_BUS 0
#define FSL_SAI_MCTL_MSEL_MCLK1 BIT(24)
#define FSL_SAI_MCTL_MSEL_MCLK2 BIT(25)
#define FSL_SAI_MCTL_MSEL_MCLK3 (BIT(24) | BIT(25))
#define FSL_SAI_MCTL_DIV_EN BIT(23)
#define FSL_SAI_MCTL_DIV_MASK 0xFF