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four tlv320aic33 with imx8 configure

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four tlv320aic33 with imx8 configure

‎05-08-2024 12:05 AM
2,036 次查看
xswyzao
Contributor II

hi, 

  i connect 4 tlv320 codec with imx8,but don't know how to confiugre dtb。

whether this connection method is ok?  

whether one tlv320 must using one sai,for example sai1 sai2 sai3 sai4

tlv.png

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‎06-03-2024 06:43 PM
1,600 次查看
pengyong_zhang
NXP Employee
NXP Employee

Hi, @xswyzao 

Their dts looks good to me.

B.R

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‎06-02-2024 11:31 PM
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pengyong_zhang
NXP Employee
NXP Employee

Hi, @xswyzao 

Could you attach your file, Don't copy all the code into the webpage

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‎06-02-2024 11:40 PM
1,630 次查看
xswyzao
Contributor II

hi,

    this is my two dts configure file

myimx8mmek240.dts
myimx8mmek240(1).dtsi
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‎06-02-2024 07:07 PM
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pengyong_zhang
NXP Employee
NXP Employee

Hi, @xswyzao 

Please share the completed updated dts file.

 

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‎06-02-2024 07:15 PM
1,658 次查看
xswyzao
Contributor II
myimx8mmek240.dtsi file
 
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2020 NXP
 */
 
/dts-v1/;
 
#include <dt-bindings/usb/pd.h>
#include "imx8mm.dtsi"
 
/ {
chosen {
stdout-path = &uart2;
};
 
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
};
 
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_led>;
 
status {
label = "status";
gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
};
 
pcie0_refclk: pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
 
 
sound-micfil {
compatible = "fsl,imx-audio-micfil";
model = "imx-audio-micfil";
cpu-dai = <&micfil>;
};
 
};
 
&A53_0 {
cpu-supply = <&buck2_reg>;
};
 
&A53_1 {
cpu-supply = <&buck2_reg>;
};
 
&A53_2 {
cpu-supply = <&buck2_reg>;
};
 
&A53_3 {
cpu-supply = <&buck2_reg>;
};
 
 
&ecspi2 {
#address-cells = <1>;
#size-cells = <0>;
fsl,spi-num-chipselects = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
status = "okay";
 
spidev0: spi@0 {
reg = <0>;
compatible = "rohm,dh2228fv";
spi-max-frequency = <500000>;
};
};
 
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
 
mdio {
#address-cells = <1>;
#size-cells = <0>;
 
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
at803x,led-act-blind-workaround;
at803x,eee-okay;
at803x,vddio-1p8v;
// eee-broken-1000t;
// rtl821x,clkout-disable;
};
};
};
 
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
 
pmic_nxp: pca9450@25 {
compatible = "nxp,pca9450a";
reg = <0x25>;
pinctrl-0 = <&pinctrl_pmic>;
pinctrl-names = "default";
interrupt-parent = <&gpio1>;
interrupts = IRQ_TYPE_LEVEL_LOW>;
 
regulators {
buck1_reg: BUCK1 {
regulator-name = "BUCK1";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
nxp,dvs-run-voltage = <850000>;
nxp,dvs-standby-voltage = <800000>;
};
 
buck2_reg: BUCK2 {
regulator-name = "BUCK2";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
 
buck3_reg: BUCK3 {
regulator-name = "BUCK3";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
};
 
buck4_reg: BUCK4 {
regulator-name = "BUCK4";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
 
buck5_reg: BUCK5 {
regulator-name = "BUCK5";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
 
buck6_reg: BUCK6 {
regulator-name = "BUCK6";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
 
ldo1_reg: LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
 
ldo2_reg: LDO2 {
regulator-name = "LDO2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
regulator-always-on;
};
 
ldo3_reg: LDO3 {
regulator-name = "LDO3";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
 
ldo4_reg: LDO4 {
regulator-name = "LDO4";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
 
ldo5_reg: LDO5 {
regulator-name = "LDO5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
};
};
};
 
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
 
};
 
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
 
tlv320aic33: tlv320aic33@18 {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic33";
reg = <0x18>;
status = "okay";
ai3x-micbias-vg = <1>; /* MICBIAS output is powered to 2.0V */
};
 
tlv320aic33a: tlv320aic33@19 {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic33";
reg = <0x19>;
status = "okay";
ai3x-micbias-vg = <1>; 
};
 
tlv320aic33b: tlv320aic33@1a {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic33";
reg = <0x1a>;
status = "okay";
ai3x-micbias-vg = <1>; 
};
 
tlv320aic33c: tlv320aic33@1b {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic33";
reg = <0x1b>;
status = "okay";
ai3x-micbias-vg = <1>; 
};
 
};
 
 
&micfil {
pinctrl-names = "default";
/* pinctrl-0 = <&pinctrl_pdm>;*/
assigned-clocks = <&clk IMX8MM_CLK_PDM>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <196608000>;
status = "disabled";
};
 
 
&pcie0{
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
disable-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
<&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_PHY>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
  <&clk IMX8MM_CLK_PCIE1_PHY>,
  <&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <100000000>, <250000000>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_100M>,
<&clk IMX8MM_SYS_PLL2_250M>;
ext_osc = <1>;
status = "okay";
};
 
&pcie0_ep{
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
<&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_PHY>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
  <&clk IMX8MM_CLK_PCIE1_PHY>,
  <&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <100000000>, <250000000>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_100M>,
<&clk IMX8MM_SYS_PLL2_250M>;
ext_osc = <1>;
l1ss-disabled;
status = "disabled";
};
 
 
/*
&sai1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;
assigned-clocks = <&clk IMX8MM_CLK_SAI1>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
status = "okay";
};
 
 
&sai2 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
status = "disabled";
};
*/
 
&sai1 {
pinctrl-names = "default", "dsd";
pinctrl-0 = <&pinctrl_sai1>;
/* pinctrl-1 = <&pinctrl_sai1_dsd>;*/
assigned-clocks = <&clk IMX8MM_CLK_SAI1>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <49152000>;
clocks = <&clk IMX8MM_CLK_SAI1_IPG>, <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_CLK_SAI1_ROOT>, <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>,
<&clk IMX8MM_AUDIO_PLL2_OUT>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
fsl,sai-multi-lane;
fsl,dataline,dsd = <0 0xff 0xff 2 0xff 0x11>;
dmas = <&sdma2 0 25 0>, <&sdma2 1 25 0>;
status = "okay";
};
 
/*
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
status = "okay";
};
 
&sai5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai5>;
assigned-clocks = <&clk IMX8MM_CLK_SAI5>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <49152000>;
clocks = <&clk IMX8MM_CLK_SAI5_IPG>, <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_CLK_SAI5_ROOT>, <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>,
<&clk IMX8MM_AUDIO_PLL2_OUT>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
fsl,sai-asynchronous;
status = "disabled";
};
*/
 
&sai6 {
fsl,sai-monitor-spdif;
fsl,sai-asynchronous;
status = "okay";
};
 
&snvs_pwrkey {
status = "okay";
};
 
&spdif1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spdif1>;
assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>,
<&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>;
clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3",
"rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k";
status = "okay";
};
 
&uart1 { /* BT */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
assigned-clocks = <&clk IMX8MM_CLK_UART1>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
status = "okay";
};
 
&uart2 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
 
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_uart3>;
assigned-clocks = <&clk IMX8MM_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
status = "okay";
};
 
&ecspi1 {
#address-cells = <1>;
#size-cells = <0>;
fsl,spi-num-chipselects = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1_spi1>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
status = "okay";
 
can: mcp2510@0 {
compatible = "microchip,mcp2510";
reg = <0>;
clocks = <&osc_20m>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can_int>;
interrupt-parent = <&gpio2>;
interrupts = <7 GPIO_ACTIVE_HIGH>;
spi-max-frequency = <2500000>;
status = "okay";
};
};
 
&usbotg1 {
dr_mode = "peripheral";
status = "okay";
};
 
&usbotg2 {
    /* USB2514 */
    dr_mode = "host";
    status = "okay";
};
 
&usdhc2 {
assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
status = "okay";
};
 
&vpu_g1 {
status = "okay";
};
 
&vpu_g2 {
status = "okay";
};
 
&vpu_h1 {
status = "okay";
};
 
&vpu_v4l2 {
status = "okay";
};
 
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
 
&gpu {
status = "okay";
};
 
&pwm1 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_gpio1_pwm1>;
status = "okay";
};
 
&pwm2 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_gpio1_pwm2>;
status = "okay";
};
 
&pwm3 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_gpio1_pwm3>;
status = "okay";
};
 
&pwm4 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_gpio1_pwm4>;
status = "okay";
};
 
&iomuxc {
pinctrl_gpio: gpio_grp {
    fsl,pins = <
        MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0     0x41
        MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27    0xd6
        MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28    0xd6
        MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29    0xd6
        MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5    0xd6
    >;
};
 
// pinctrl_mipi_dsi: mipi_dsi_grp {              /* dsi, 2023.05.12 check */
    // fsl,pins = <
        // MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1       0x41    /* DSI:BL */
        // MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8       0x16    /* DSI:EN */
        // MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12      0x16    /* DSI:WAKE */
    // >;
// };
 
pinctrl_touch: touch_grp {       /* dsi, 2023.03.05 check */
    fsl,pins = <
        MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9       0x19    /* TS:INT */
        MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1         0x41    /* TS:RST */
    >;
};
 
pinctrl_gpio1_pwm1: gpio1_pwm1_grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT    0x16
>;
};
 
pinctrl_gpio1_pwm2: gpio1_pwm2_grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO13_PWM2_OUT    0x16
>;
};
pinctrl_gpio1_pwm3: gpio1_pwm3_grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO14_PWM3_OUT    0x16
>;
};
pinctrl_gpio1_pwm4: gpio1_pwm4_grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT    0x16
>;
};
 
pinctrl_rtc_int: rtcintgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19
>;
};
 
pinctrl_csi_pwn: csi_pwn_grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
>;
};
 
pinctrl_csi_rst: csi_rst_grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
>;
};
 
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
>;
};
 
pinctrl_ecspi2_cs: ecspi2cs {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000
>;
};
 
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
>;
};
 
pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
>;
};
 
pinctrl_gpio_wlf: gpiowlfgrp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6
>;
};
 
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
 
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
 
pinctrl_i2c2_synaptics_dsx_io: synaptics_dsx_iogrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9               0x19    /* Touch int */
>;
};
 
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
};
 
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 /* open drain, pull up */
MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41
MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41
>;
};
 
/* pinctrl_pdm: pdmgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6
MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0xd6
MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6
MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0xd6
MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0xd6
MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0xd6
MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0xd6
>;
}; */
 
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
>;
};
 
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
};
 
pinctrl_sai1: sai1grp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6
MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 
/* MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6*/
MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6
MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6
MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6
MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6
MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6
MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0    0xd6
MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1    0xd6
MX8MM_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2    0xd6
MX8MM_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3    0xd6
>;
};
 
/*
pinctrl_sai1_dsd: sai1grp_dsd {
fsl,pins = <
MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6
MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6
MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6
MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6
MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6
MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6
MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6
MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6
MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6
MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6
MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6
>;
};
*/
pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK      0xd6
MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC     0xd6
MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0    0xd6
>;
};
 
pinctrl_sai2_dsi_rst: sai2_dsi_rst_grp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x41
>;
};
 
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
            MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0     0xd6
            MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10       0xd6    /* WM8960:INT */
>;
};
 
pinctrl_sai5: sai5grp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6
MX8MM_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6
MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6
MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6
MX8MM_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1    0xd6
            MX8MM_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2    0xd6
            MX8MM_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3    0xd6
>;
};
 
pinctrl_spdif1: spdif1grp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
>;
};
 
pinctrl_typec1: typec1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
>;
};
 
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX     0x140
MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX     0x140
>;
};
 
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>;
};
 
pinctrl_uart3_uart3: uart3uart3grp {
fsl,pins = <
MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX  0x140
MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX  0x140
>;
};
 
pinctrl_spi1_spi1: spi1spi1grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x13
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13
>;
};
 
pinctrl_usdhc1_gpio: usdhc1grpgpio {
fsl,pins = <
MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
>;
};
 
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
>;
};
 
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
>;
};
 
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
>;
};
 
pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
fsl,pins = <
            MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x1c4
            MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12    0x1c4
>;
};
 
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
 
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
 
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
 
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
 
pinctrl_can_int: spi_can_int {
fsl,pins = <
MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x41
>;
};
};

------------------------------------------------------------------------------------------------

myimx8mmek240.dts

 

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2023 MYZR
 */
 
/dts-v1/;
 
#include <dt-bindings/usb/pd.h>
#include "myimx8mmek240.dtsi"
 
/ {
model = "MYZR i.MX8M Mini EK240 board";
compatible = "myzr,myimx8mmek240", "fsl,imx8mm-evk", "fsl,imx8mm";
 
 
clocks {
osc_20m: clock@6 {
compatible = "fixed-clock";
/*reg = <0x7>;*/
#clock-cells = <0>;
clock-frequency = <20000000>;
clock-output-names = "osc_20m";
};
};
 
aliases {
spi0 = &flexspi;
};
 
usdhc1_pwrseq: usdhc1_pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1_gpio>;
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
};
 
sound1: sound1 {
compatible = "simple-audio-card";
simple-audio-card,name = "TLV320AIC3x-Card";
simple-audio-card,widgets =
"Line", "Line In Jack",
"Line", "Line Out Jack";
simple-audio-card,routing =
"LINE1L", "Line In Jack",
"LINE1R", "Line In Jack",
"Line Out Jack", "LLOUT",
"Line Out Jack", "RLOUT";
 
simple-audio-card,format = "dsp_b";
simple-audio-card,bitclock-master = <&sound1_master>;
simple-audio-card,frame-master = <&sound1_master>;
simple-audio-card,bitclock-inversion;
 
cpudai: simple-audio-card,cpu {
sound-dai = <&sai1>;
};
 
sound1_master: simple-audio-card,codec {
sound-dai = <&tlv320aic33>,<&tlv320aic33a>,<&tlv320aic33b>,<&tlv320aic33c>;
system-clock-frequency = <49152000>;
clocks = <&clk IMX8MM_CLK_SAI1_ROOT>;
};
};
 
};
 
 
&ddrc {
operating-points-v2 = <&ddrc_opp_table>;
 
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
 
opp-25M {
opp-hz = /bits/ 64 <25000000>;
};
 
opp-100M {
opp-hz = /bits/ 64 <100000000>;
};
 
opp-750M {
opp-hz = /bits/ 64 <750000000>;
};
};
};
 
&flexspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi>;
status = "okay";
 
flash@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <80000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
};
};
 
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wlan>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wlan>;
bus-width = <4>;
keep-power-in-suspend;
non-removable;
wakeup-source;
mmc-pwrseq = <&usdhc1_pwrseq>;
fsl,sdio-interrupt-enabled;
status = "okay";
 
wifi_wake_host {
compatible = "nxp,wifi-wake-host";
interrupt-parent = <&gpio2>;
interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "host-wake";
};
};
 
&usdhc3 {
assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
 
 
/*
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
 
tlv320aic3106: tlv320aic3106@18 {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic33";
reg = <0x1a>;
status = "okay";
ai3x-micbias-vg = <1>; 
};
 
};
*/
 
&iomuxc {
 
pinctrl_flexspi: flexspigrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK               0x1c2
MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B            0x82
MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0           0x82
MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1           0x82
MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2           0x82
MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3           0x82
>;
};
 
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x190
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d0
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d0
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d0
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d0
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d0
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d0
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d0
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d0
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x190
>;
};
 
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x194
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d4
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d4
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d4
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d4
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d4
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d4
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d4
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d4
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d4
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x194
>;
};
 
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x196
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d6
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d6
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d6
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d6
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d6
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d6
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d6
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d6
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d6
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x196
>;
};
 
pinctrl_wlan: wlangrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141
MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x159
>;
};
};

 

 

 

 

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回复

‎05-28-2024 08:10 PM
1,706 次查看
pengyong_zhang
NXP Employee
NXP Employee

Hi, @xswyzao 

I didn't find the node sound-tlv320aic33, which should connect sai1 to the codec.

Is it defined in another file?

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回复

‎05-29-2024 06:01 PM
1,700 次查看
xswyzao
Contributor II
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
 
tlv320aic33: tlv320aic33@18 {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic33";
reg = <0x18>;
status = "okay";
ai3x-micbias-vg = <1>; /* MICBIAS output is powered to 2.0V */
};
 
tlv320aic33a: tlv320aic33@19 {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic33";
reg = <0x19>;
status = "okay";
ai3x-micbias-vg = <1>; 
};
 
tlv320aic33b: tlv320aic33@1a {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic33";
reg = <0x1a>;
status = "okay";
ai3x-micbias-vg = <1>; 
};
 
tlv320aic33c: tlv320aic33@1b {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic33";
reg = <0x1b>;
status = "okay";
ai3x-micbias-vg = <1>; 
};
 
};
 
it defined in myimx8mmek240.dtsi,
 
i using confiure:
sound1_master: simple-audio-card,codec {
sound-dai = <&tlv320aic33>;
system-clock-frequency = <49152000>;
clocks = <&clk IMX8MM_CLK_SAI1_ROOT>;
one tlv320 codec can play。
 
i updated as follows:
sound-dai = <&tlv320aic33>,<&tlv320aic33a>,<&tlv320aic33b>,<&tlv320aic33c>;
 
Is this confiure correct?
 
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‎05-28-2024 07:52 PM
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pengyong_zhang
NXP Employee
NXP Employee

Hi, @xswyzao 

The ak4458 is used in the Audio Board, see https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-developm...

The schematic can be found in i.MX Audio Board Design Files in the same page.

B.R

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‎05-22-2024 07:03 PM
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pengyong_zhang
NXP Employee
NXP Employee

hi, @杨振伟 

Sorry for reply late.

It is OK to connect 4 codecs to same SAI.

You can refer to arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi:

1. in node sound-ak4458, it uses two ak4458 codecs: ak4458_1 and ak4458_2. 

2. in node sai1, it should be same.

3. in pinctrl_sai1, just add MX8MM_IOMUXC_SAI1_RXDx_SAI1_RX_DATAx (here x means 0~7).

B.R

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‎05-28-2024 06:50 PM
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xswyzao
Contributor II

hi:

    i  imitate imx8mm-evk.dtsi, writed a dts for 4 tlv320aic33 using sai1，could u help review it?

myimx8mmek240.dts
myimx8mmek240.dtsi
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‎05-23-2024 06:47 PM
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xswyzao
Contributor II
hi,pengyong:
Where can I find the schematic for imx8mm-evk with ak4458
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‎05-13-2024 01:38 AM
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杨振伟
Contributor I

We will create a device that can play 7.1 channels music.

If play 8-channel music, it is OK. Can you provide a reference DTS file?

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‎05-10-2024 06:23 PM
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pengyong_zhang
NXP Employee
NXP Employee

Hi, @杨振伟 

I know you need connect more encoding and decoding chips, But what is your purpose? 

For example, If you play 8-channel music, it is OK, and each codec is responsible for two channels.But if you want to play four songs and expect each codec to be responsible for one song, you can't

B.R

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‎05-13-2024 01:20 AM
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杨振伟
Contributor I

We will create a device that can play 7.1 channels music.

If play 8-channel music, it is OK. Can you provide a reference DTS file?

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‎05-09-2024 02:18 AM
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杨振伟
Contributor I

1.  Our product needs to be equipped with more encoding and decoding chips.

2.  i.MX 8M Mini Applications Processor Reference Manual

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‎05-09-2024 12:19 AM
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pengyong_zhang
NXP Employee
NXP Employee

Hi, @xswyzao 

What your purpose for connect four tlv320 with one SAI?

one sai connect four tlv320aic33 by TDM(time division multiplexing).
we have noticed that SAI1 supports this feature

>>> Where are you fuund this?

B.R

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‎05-08-2024 07:25 PM
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pengyong_zhang
NXP Employee
NXP Employee

Hi, @xswyzao 

What is your BSP version?I think you can follow the below link check if your HW connect is reght.

https://community.nxp.com/t5/i-MX-Processors/How-to-enable-TLV320-on-IMX6Q/m-p/304913

whether one tlv320 must using one sai,for example sai1 sai2 sai3 sai4

>>> Yes, one to one.

B.R

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‎05-08-2024 10:00 PM
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xswyzao
Contributor II
one sai connect four tlv320aic33 by TDM(time division multiplexing).
we have noticed that SAI1 supports this feature
please confirm again，ths。
this is one codec with 4 i2s:
https://community.nxp.com/t5/i-MX-Processors/iMX8MP-SAI1-audio-path-playback-configuration/td-p/1670...
whether we modify driver,write 4 tlv320 as one 4 channel device? we using 5.10.72 kernel
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‎05-08-2024 12:34 AM
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xswyzao
Contributor II

this is my dts

myimx8mmek240.dts
myimx8mmek240.dtsi
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