iMX8MP SAI1 audio path playback configuration

[RVT]

Hello,

The hardware configuration of our product as shown below. The SAI1 TXD0,1,2 are input to a multi-input channels codec. The audio playback from SAI1_TXD0 to CX_SDIN1 is successful by using speaker_test.

I would like to know how to test the path from SAI1_TXD1/SAI1_TXD2 to CX_SDIN2/CS_SDIN3 respectively.

Thanks.

[Dhruvit]

Hi @RVT,

I hope you are doing well.

I would like to know how to test the path from SAI1_TXD1/SAI1_TXD2 to CX_SDIN2/CS_SDIN3 respectively.

=> To test the different SAI data lines one can configure that line from the device tree according to section 8.1.1.1 Muxing Options from the reference manual IMX8MPRM. 

Please refer to the file fsl_sai.txt to configure the SAI in the device tree.

More information related to the same can be found in section 14.1.1 Audio Interface from the reference manual.

The available test for the audio can be referred from section 11.6 Audio from the i.MX Linux Reference Manual.

Thanks & Regards,

Dhruvit Vasavada

[RVT]

Hello @Dhruvit ,

sai1 was defined in dts as following:

&sai1 {
compatible = "fsl,imx8mp-sai";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;
assigned-clocks = <&clk IMX8MP_CLK_SAI1>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_IPG>, <&clk IMX8MP_CLK_DUMMY>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_MCLK1>, <&clk IMX8MP_CLK_DUMMY>,
<&clk IMX8MP_CLK_DUMMY>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
fsl,sai-synchronous-rx;
dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
dma-names = "rx", "tx";
fsl,dataline = <1 0x0f 0x0f>;
status = "okay";
};

pinctrl_sai1: sai1grp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_TXFS__AUDIOMIX_SAI1_TX_SYNC 0xd6
MX8MP_IOMUXC_SAI1_TXC__AUDIOMIX_SAI1_TX_BCLK 0xd6
MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0xd6
MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_SAI1_RX_DATA01 0xd6
MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_SAI1_RX_DATA02 0xd6
MX8MP_IOMUXC_SAI1_TXD0__AUDIOMIX_SAI1_TX_DATA00 0xd6
MX8MP_IOMUXC_SAI1_TXD1__AUDIOMIX_SAI1_TX_DATA01 0xd6
MX8MP_IOMUXC_SAI1_TXD2__AUDIOMIX_SAI1_TX_DATA02 0xd6
>;
};

With this SAI1 dts, we tried the following commands but only SAI1_TXD0 has output signal by measurement.

aplay --device=hw:0,0 test.wav -c1
aplay --device=hw:0,0 test.wav -c2
aplay --device=hw:0,0 test.wav -c3
aplay --device=hw:0,0 test.wav -c4

speaker-test -Dhw:0,0 -t sine -f 1000
speaker-test -Dhw:0,0 -t sine -f 1000 -c3 -s1
speaker-test -Dhw:0,0 -t sine -f 1000 -c3 -s2
speaker-test -Dhw:0,0 -t sine -f 1000 -c3 -s3
speaker-test -Dhw:0,0 -t sine -f 1000 -c4 -s4

Thanks.

[Dhruvit]

Hi @RVT,

I hope you are doing well

My apology for the delayed response.

If possible kindly share your audio test file(test.wav) and the whole device tree file to further debug the issue.

Thanks & Regards,
Dhruvit Vasavada

[RVT]

Hello @Dhruvit ,

In the last couple of days, all three D/A audio path of this codec were proved with analog audio output by wiring SAI1 TXD0 to codec DIN2 and DIN3 respectively. Unfortunately, we still cannot get TXD1 & 2 with digital output. FYI, the DA audio path in this codec is not required to route by setting register. So, there should be analog audio output as long as there is a corresponding digital input.

Please find the attached dts file and test.wav. Hope the solution can be available by end of this week.

Thank you very much.

[Dhruvit]

Hi @RVT,

I hope you are doing well

It seems that the audio can be routed to multi-channel from the driver only.

We recommend you debug the sai driver from the Linux source code.

sound/soc/fsl/fsl_sai.c

Further, kindly refer to section 14.4.2.4.4 FIFO Combine from the Reference Manual IMX8MPRM.

"FIFO Combining mode allows the separate FIFOs for multiple data channels to be used

as a single FIFO for either software accesses or a single data channel or both. Note that
the enabled data channels must be contiguous and data channel 0 must be enabled when
using FIFO Combine mode."

After this, We would recommend you test with different audio test files. As sometimes it depends on the characteristics of the audio file also.

Thanks & Regards,
Dhruvit Vasavada

[RVT]

Hi @Dhruvit ,

I tried to enable "FIFO Combining mode" by modifying as following in "fsl_sai.c". But it didn't work. Please advise.

sai->is_multi_fifo_dma = false;

regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), FSL_SAI_CR4_FCOMB_MASK, FSL_SAI_CR4_FCOMB_SOFT);

Thanks.

[Dhruvit]

Hi @RVT,

I hope you are doing well

My sincere apology for the delayed response.

Please find some more information regarding the same.

Please refer to the below link for the information related to the audio codec interface with the IMX8 board.

https://www.digi.com/resources/documentation/digidocs/embedded/dey/3.2/cc8mmini/bsp_r_audio_8m

For more information regarding the same query, please refer to the below thread.

https://community.nxp.com/t5/i-MX-Processors/Configuring-SAI-for-I2S-multi-line-with-linux/m-p/13122...

https://community.nxp.com/t5/i-MX-Processors/How-to-use-i-MX8mm-sai-multi-lane/m-p/917438

I hope this information will help you towards configuring the SAI multiline.

Thanks & Regards,
Dhruvit Vasavada

[RVT]

Hi @Dhruvit ,

Thanks for your information on iMX8MM.

We cannot get a positive result with those configuration and other similar cases in NXP forum. Those cases were not solved in the forum and also not directly related to iMX8M plus. Also, I cannot find any case on iMX8MP about SAI multi-lane with solution in the forum.

I believe NXP should have a demonstration configuration & code for SAI multi-lane (output via TXD0, 1, 2,.....) or output at individual TXD pin because it is a feature in iMX8MP that NXP should have something to validate its feature. In my case as described before, it is not related to codec part because it was proved that all audio paths of this codec were routed properly with audio output. It's a matter how to let SAI1 TXD1/2/3 output signal.

It would be appreciated if NXP expert like you could provide a total solution (dts configuration, related kernel code, related kernel version) for SAI multi-lane (output via TXD0, 1, 2,.....) or at least output at individual TXD pin. Thank you very much.