fetch rx uart stream with sdma

[larstraeger]

Hello,

i want to fetch a continuous Uart Stream over a SDMA Channel. The common Packet size is greater then 32Bytes.

Until now i manage to build my own sdma script that is triggert by the uart rx dma request. I use UART2, so that i'm working with the Peripheral Funktion Unit to fetch the data and the Burst Unit to store the data in my memory. All works fine with Packet sizes under 32Bytes.

The Problem is now, when i transmit Packets greater then 32 Bytes ,the UART FIFO overruns and the tailing data will be dropped. For me it seems that the procedure--> generate dma request/ trigger as runnable channel / load context/ run channel,  takes so long, that the UART FIFO is already full and begin to drop data. I test it with 9600 Baud-rate but the same Problem occurs. I also test it with a running dma channel that read the rx fifo and store it in memory when value is valid (check CHARRDY flag) to omit the context switches etc. But every time i get an Overrun issue.

My Question is now, is my Goal possible and somebody done this work already. if so, could  i achieve fetching continuous Uart Streams till 1-4MHZ?

some hints will be very helpful.

regards

lars

[israelpz]

Hi,

Which i.mx are you using?

i don't know if is possible but packet bigger than 32 bytes are common for protocol over uart like Bluetooth and they are handled fine using the ROM scripts.I suspose the FIFO threshold is 32 bytes and  seem the script you are using is not retrieving all the bytes before the FIFO threshold is hit.

I had been using the uart at 1 mbps and 2 mbps with audio streams which are packet of from 200 bytes to 1k  using the ROM scripts. Of couse the DMA transfers are not of that size but i never had overruns.

I don't know if somebody had been able to run  at 1 or 4 MHZ  the trasnfer of the DMA uart but i could ask.

Maybe you could try to use the cache L2(OSRAM) as destiny for those DMA transfer instead the DRAM.

Regards,

-Israel.

[larstraeger · Accepted solution]

Hello and thanks for the response,

"Which i.mx are you using?"

i use the i.mx535.

Now the problem is solved for me. I manage to handle streams @4MHZ Baud

over the "shared Uart". The seems to be faster then normal Uarts in DMA

Request handling etc.

" Maybe you could try to use the cache L2(OSRAM) as destiny for those DMA

transfer instead the DRAM."

This is i not try until today but i will be when i tune my implementation.

Regards

lars

2013/4/8 Israel Perez Gonzalez <admin@community.freescale.com>

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Perez Gonzalez <https://community.freescale.com/people/israelpz> in *i.MX

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[nodeax]

Hi Iars,

Is it possible to share your SDMA script and any modifications you needed to do to the UART/DMA driver?

Thanks,

Akshay

[YixingKong]

Traeger, if your question had been answered please click Correct Answer, so that we can close your DI.

Thanks,

Yixing