eim negative timing parameters

[fpgaace]

I believe I understand what's intended but being relatively new to the EIM interface I'd like to be sure before designing to it.  I'm referencing the Figure 12 waveforms and Table 42 bus timing parameters in i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 3

Using timing parameter WE4 for example, and t=10ns, WE4 = -3.25ns which is negative.  If you map WE4 onto the waveform it shows address becoming valid before the rising edge of BCLK by a negative 3.25ns.  However the WE4 description says, "Clock rise to address valid" which is saying the address becomes valid after the rising edge.  So, the parameter description and waveform don't match with one another, and the parameter value is negative.

If I leave the waveform alone and convert the WE4 parameters to positive values (plus flipping min/max) then I assume that's the right timing.  Can someone confirm and clarify this for me please?

Thanks, and sorry for the dumb question.

Mike.

[igorpadykov]

Hi mike

document uses formal mathematical language

WE4 "Clock rise to address valid" = Taddress valid - Tclock rise .

You can consider expression "to address valid" as reference point for

T - absolute time in absolute time graph. So if clock comes later (as in Figure 12),

its time is bigger than Taddress valid, which gives negative value using

this formula.

However using common sense and understanding of EIM operation

one can ignore minus/plus results.

Best regards

igor

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------

[fpgaace]

Thanks Igor,

So to be clear, address is valid BEFORE the rising edge of BCLK.  Correct?

[igorpadykov]

Hi mike

yes, correct.

Best regards

igor