custom imx8mp fastboot flash uboot error

[hjk003]

Hi, nxp team. We are using our own customized version based on imx8mp-evk, with the boot mode set to SDPS. An error occurred when flashing uboot; we wanted it to be flashed to eMMC, but it didn't. Below is the error message:

Unknown image format!
Run fastboot
(NULL udevice *): request 00000000fcf12640 was not queued to ep1in-bulk
Starting download of 1701840 bytes
(NULL udevice *): request 00000000fcf12640 was not queued to ep1in-bulk
............
downloading of 1701840 bytes finished
(NULL udevice *): request 00000000fcf12640 was not queued to ep1in-bulk
Not support flash command for current device 255
(NULL udevice *): request 00000000fcf12640 was not queued to ep1in-bulk

He suggested `Not support flash command for current device 255`

[pengyong_zhang]

Hi @hjk003 

Please create another ticket talk about this new question. 

B.R

[pengyong_zhang]

Hi @hjk003 

What is your flash tool? we suggest you use our UUU tool flash the Image to your EMMC.

B.R

[hjk003]

@pengyong_zhang , Hi, We've solved that problem, but we have another question about the SJA1105P. Our board's general structure and device tree are as follows. We use ethernet0 for external communication, ethernet1's MAC address is directly connected to port 2 of the SJA1105P, and the other four ports are also in use. What modifications are needed to the device tree based on the imx8mp-evk? Thank you for your reply.

        ┌──────────────────────────────┐
        │                              │
        │                              │
        │                              │
        │                              │
        │                              │
        │                  ┌───────────┴───────────────┐
        │                  │         SPI               │
  ┌─────▼─────────┐        │                           │
  │   SPI         │        │                           │
  │ port0         │        │M                          │
  │ port1    port2◄────────┤A                          │
  │    SJA1105    │        │C                          │
  │               │        │1       CPU                │
  │ port3         │        │   MIMX8ML8DVNLZAB         │
  │ port4         │        │                           │
  │               │        │                           │
  └─────── ───────┘        │                           │
                           │        MAC2               │
                           └──────────┬────────────────┘
                                      │
                                      │
                                      │
┌───────── ────────┐                  │
│       RGMII      │                  │
│                  │                  │
│   PHY            │                  │
│   88E1512       M│                  │
│                 D◄──────────────────┘
│                 I│
│                 O│
│                  │
└───────┬──────────┘
        │
        │
        │
        │
        │
        │
        │
        │
        │
        └► OUT

			eqos: ethernet@30bf0000 {
				compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
				reg = <0x30bf0000 0x10000>;
				interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "macirq", "eth_wake_irq";
				clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
					 <&clk IMX8MP_CLK_QOS_ENET_ROOT>,
					 <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
					 <&clk IMX8MP_CLK_ENET_QOS>;
				clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
				assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
						  <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
						  <&clk IMX8MP_CLK_ENET_QOS>;
				assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
							 <&clk IMX8MP_SYS_PLL2_100M>,
							 <&clk IMX8MP_SYS_PLL2_125M>;
				assigned-clock-rates = <0>, <100000000>, <125000000>;
				nvmem-cells = <&eth_mac2>;
				nvmem-cell-names = "mac-address";
				intf_mode = <&gpr 0x4>;
				status = "disabled";
			};
		};

&iomuxc {	
pinctrl_eqos: eqosgrp {
		fsl,pins = <
			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x2
			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x2
			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x90
			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x90
			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x90
			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x90
			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90
			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x90
			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x16
			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x16
			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x16
			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x16
			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x16
			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16
			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22				0x10
		>;
	};
};

&eqos {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_eqos>;
  status = "okay";
};

&ecspi1 {  // switch & imu

	fsl,spi-num-chipselects = <3>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1>;
	cs-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>,		// CS 0 switch 
							<&gpio1 14 GPIO_ACTIVE_LOW>,	 
							<&gpio1 10 GPIO_ACTIVE_LOW>;	
	status = "okay";

	sja1105p@0 {
    #address-cells = <1>;
    #size-cells = <0>;
		compatible = "nxp,sja1105p";
		firmware_name = "sja1105p_cfg.bin"; /// optional 
		spi-max-frequency = <0x17d7840>;  // 25 000 000 
		spi-cpha;
		reg = <0x0>;

		port-0 {
			is-host = <0x0>;
			null-phy = <0x1>;
			phy-ref = < 0 >;
			logical-port-num = < 0 >;
		};

		port-1 {
			is-host = <0x0>;
			null-phy = <0x1>;
			phy-ref = < 0 >;
			logical-port-num = < 0xff >;
		};

		port-2 {
      label = "cpuMAC";
      phy-mode = "rgmii-id";
			is-host = <0x1>;
			null-phy = <0x0>;
			phy-ref = <0>;
			logical-port-num = < 1 >;

      ethernet = <&eqos>;
      fixed-link {
        speed = <1000>;
        full-duplex;
      };
		};

		port-3 {
			is-host = <0x0>;
			null-phy = <0x0>;
			phy-ref = <0>;
			logical-port-num = < 2 >;
		};

		port-4 {
			is-host = <0x0>;
			null-phy = <0x0>;
			phy-ref = <0>;
			logical-port-num = < 3 >;
		};
	};

	imu_accel@1 {
		reg = <1>;
		compatible = "SMI230ACC";
		cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
	};
	imu_gyro@2 {
		reg = <2>;
		compatible = "SMI230GYRO";
		cs-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
	};
};