boot strapping timing

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boot strapping timing

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inmaku
Contributor III

What is the Timing relation ship between sampling the i.MX6 GPIOs for boot strapping and the POR_B Signal? What are teh Setup/hold requirements?

Thanks,

Ingo

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Yuri
NXP Employee
NXP Employee

I am afraid - no, this information is not provided in documentation.

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Yuri
NXP Employee
NXP Employee


The boot mode pins are read at 300us to 1ms after reset is deasserted,

therefore if buffers are used to isolate the boot pins, they should be

enabled for 1-10 ms after reset negation.


Have a great day,
Yuri

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inmaku
Contributor III

Hi Yuri,

Thanks - that is what I needed. Can I find this Information in the reference Manual or data sheet?

Thanks,

Ingo

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Yuri
NXP Employee
NXP Employee

I am afraid - no, this information is not provided in documentation.

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inmaku
Contributor III

After your posting I did remember one reference design making this statement: The MCIMX6SLEVK board has this note on page 13.

With this  - I guess - I have to take the word on it.

Thanks!