Worst case internal power consumption for iMX8MQ

[riteshpatel]

Hi,

We are working on iMX8MQ based custom board. We have calculated the internal worst-case power consumption on iMX8MQ processor using NXP iMX8MQ EVK board as a reference. We understand that the typical power consumption depends on the use case.

The EVK power consumption value derived from the above calculation is too high (~14.8W).

We found one application note, AN12118, which shows the power consumption of iMX8M processor is <4W.

So we want to understand, why the EVK power distribution is designed for such high power, ~14.8W?

We do not want to over budget our power supply design for iMX8MQ processor. 

Thanks.

[art]

The worst case power consumption umbers can be calculated from the maximum supply current numbers for various power rails, given in the Table 9 of the i.MX8M Data Sheet document, available on the processor's Documentation web page:

https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-appl...

Have a great day,
Artur

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[bernhardfink]

I assume you used the maximum values of Table 9 in the 8M Data Sheet for this calculation.

This a very very pessimistic approach for an overall maximum power consumption.

Let me provide some explanations:

• The chapter talks about "power supply design", this includes all elemts of a power suplly. The source itself, the discrete decoupling capacitors and the capacitance you have inside the PCB structure.
• The maximum requirement of a power domain input is determined by the number of silicon gates which toggle in this domain. In an ideal world you would be able to determine the max current using some silicon technology parameters (capacitance of each gate + number of gates toggling at the same time).
• In the real world you also have inductors which you don't want, but they are there. So you need to put a little bit on top.
• So we take a specific maximum of gates + the parasitics and calculate a max power requirement which will cover the peak consumption at the time the gates are switching. This is normally a pretty short period and not an average power consumption.
• A part of this peak current comes out of the decoupling capacitor network, which relaxes the requirement for the initial LDO or DC/DC, so finally if you have for example a max requirement of 3000mA, the power source might need to deliver 2200mA and the remaining 800mA come out of the capacitors.
• As this depends on the PCB with its "power supply design", we cannot provide such real world numbers, we can only provide max numbers based on calculation done on chip level.
• The situation that all gates of the different domains switch synchronously is not realistic, so summing up the peak current of all domains for the same point in time is not useful.
• The app note which shows the the power consumption for specific use cases is real world, and that's a completely different aspect. The Table 9 with the max power requirement gives you the basis for a stable power supply design, the app note gives you the basis for the average current consumption so that you can for example determine the capacity of your battery
• The average current consumption is also the basis for a thermal design planning

Regards,

Bernhard.

[riteshpatel]

Thank you very much Bernhard.

This is indeed a very helpful information.

Appreciate your inputs.

Thanks.