m4 timing problem ddr ? tcm

[FIDDO]

currently im using imx8 processor. im runnning autosar on m core and qnx on A core.  initially we run both a and m core from DDR and it was working fine. 

But wen i started loading big applications on A core. Performance of m core impacted badly. pit timer isr get  affected by huge margin.

as a alternative solution we move code of the m core from ddr to tcm. after doing  that,  things appeared normal even after heavier loading at the a core.

bt sadly, for a fully developed m core will have slight bigger memory to make it difficult to fit in  tcm memory [ 256 kb ].

for example, lets take my m-core memory will be of 900kb.

wats ur expert advice. how should i handle this scenario ????d

[igorpadykov]

Hi Ruby

your solution seems as correct, since ddr is used both by A core and M core.

If A actively uses ddr, then M4 may have reduced ddr bandwidth.

Probably this may be adjusted using bus arbiters (NIC/NOC) settings, however

this depends on particular application. Unfortunately I am not aware of better solutions, sorry.

Best regards
igor
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