Which is better for reference inc file in SABRE-SD

[ko-hey]

Hi all

I want to confirm which inc file is better.

There are two files for SABRE-SD.

One is MX6Q_SabreSD_DDR3_register_programming_aid_v1.5.inc.

It is in i.MX6/7 DDR Stress Test Tool V2.30 .

The other can get from "RealView .inc file" tab of MX6Q_SabreSD_DDR3_register_programming_aid_v1.9.xlsx.

That is in i.MX6DQ SABRE SDP/B DDR3 Register Programming Aid​.

Which one is better to reference ?

Ko-hey

[Yuri · Accepted solution]

Hello,

   generally, You may use any of the mentioned initialization scripts.

The Programming Aid provides ability to modify the script automatically.

Have a great day,
Yuri

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[ko-hey]

Hi

Do you mean there are no recommendation ?

Ko-hey

[Yuri]

Hi,

Do you see signicficant difference between the files ?

~Yuri.

[ko-hey]

Hi Yuri

Sorry for late reply.

> Do you see signicficant difference between the files ?

Yes, I compared both.

As a result, there are three different point.

1. Register address: 0x021b08c0

The following comment is written in both of it.

However, it's uncommented in v1.5 but it isn't uncommented in v1.9.

Which is appropriate for SABRE-SD Rev C ?

setmem /32 0x021b08c0 = 0x24911492

2. Register address: 0x021b0008

There is a difference in MMDC Core ODT Timing Control Register(MMDCx_MDOTC).

In particular, the tAOFPD and tAONPD field are different.

Which tAOFPD and tAONPD settings is appropriate for SABRE-SD Rev C ?

inc file version	Register Address	Register Value	tAOFPD	tAONPD
v 1.5	0x021B0008	0x09444040	2 cycles	2 cycles
v 1.9		0x24444040	5 cycles	5 cycles

3. Register address: 0x021b0010

There is a difference in MMDC Core Timing Configuration Register 1(MMDCx_MDCFG1)

In particular, the tRC, tRAS and tRPA field are different.

Which tRC, tRAS and tRPA settings is appropriate for SABRE-SD Rev C ?

inc file version	Register Address	Register Value	tRC	tRAS	tRPA
v 1.5	0x021b0010	0xFF538F64	27 clocks	20 clocks	tRP + 1
v 1.9		0xFF320F64	26 clocks	19 clocks	tRP

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Add info: I attached following files that I used to confirm.

・2Gb_1_35V_DDR3L.pdf

・MX6Q_SabreSD_DDR3_register_programming_aid_v1.5.inc

・MX6Q_SabreSD_DDR3_register_programming_aid_v1.9.inc

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Ko-hey

[Yuri]

Hi,

Generally it is recommended to use the recent release (1.9).

Nevertheless, the following may be useful.

1.
   As for the duty cycle ;  from old errata :

“DDR: The SDCLK and SDCLK_B signals during DDR access have
a duty cycle violation vs. JEDEC requirements - Fixed in 1.2”

2.

tAOFPD - This field determines the time between termination cuircuit starts to turn
off the ODT resistance till termination has reached high impedance. Obtain this
value from DDR3 data sheet.

tAONPD - This field determines the time between termination cuircuit gets out of high
impedance and begins to turn on till ODT resistance are fully on. Obtain this value
from DDR3 data sheet.

3.

tRC - Active to Active or Refresh command period (same bank). Obtain this value from
DDR3 data sheet.

tRPA - Precharge-all command period. Obtain this value from DDR3 data sheet.

tRAS - Active to Precharge command period (same bank). Obtain this value from
DDR3 data sheet.

Regards,

Yuri.

[ko-hey]

Hi Yuri

Thank you for your great support.

ko-hey