Which frequency is correct for i.MX6SDLACLK_EIM_SLOW_CLK_ROOT?

[satoshishimoda]

Hi community,

We have a question about i.MX6SDL CCM.

Please see Table 18-3 in IMX6SDLRM Rev.1.

It shows ACLK_EIM_SLOW_CLK_ROOT = 198MHz (default).

However, according to the initial register setting of CCM_CSCMR1, it seems to be a half of AXI clock frequency (blue line in Figure 18-2).

And according to the initial register setting of CCM_CBCDR, AXI frequency is half of a half of PLL2 396MHz.

So we can get ACLK_EIM_SLOW_CLK_ROOT = 99MHz (a quater of PLL2 396MHz).

Which is correct?

Best Regards,

Satoshi Shimoda

[Yuri]

Hello,

   For the recent RM - please refer to https://community.nxp.com/thread/442559 

Regards,

Yuri.

[Yuri · Accepted solution]

By default, EIM ACLK (aclk_eim_slow) is sourced from AXI clock root (396MHz) with divide-by-2, so it is 198 MHz.

Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[Rob_iMX6]

Hi Yuri

According to the datasheet of iMX.6SDL, ACLK_EIM_SLOW_CLK_ROOT must not exceed 132MHz (i:MX 6Solo/DualLite Rev.5, page 52).

Does this mean that the default clock is out of spec?

Best regards,

-Urs

[Yuri]

Hello,

  Looks like - yes, the default value should not be used.

Regards,

Yuri.

[satoshishimoda]

Hi Yuri,

Thank you for your reply.

According to your reply, it seems that our understanding about AXI bus frequency was wrong.

Maybe, I will create a new thread about AXI bus frequency.

Thank you.

Best Regards,

Satoshi Shimoda