i.MX6 CCM PLL audio/video numerator

[vsiles]

In the i.MX6Q ref manual, chapter about CCM, there are some numerator / denominator register for several PLL.

In the Audio PLL numerator, for example, we can read:

This register contains the numerator (A) of Video PLL fractional loop divider.(Signed number)

Also, the binary layout of the register forces bits 30 and 31 to be set to 0.

Does this mean that the numerator will alway be positive, between 0 and 2^30 - 1, or does this mean that the numerator is a signed integer of 30 bit, and I should compute the 2 complement on 30 bits (and not 32 bits as usual) ?

Could anyone clarify that please ?

Best,

V.

PS: for the record, in linux, the register is read as an uint32_t without any special treatment.

[igorpadykov · Accepted solution]

Hi Vincent

it is signed integer of 30 bit and one should compute 2 complement on 30 bits.

For example please check older i.MX, like Chapter 21 DPLL Controller (DPLLC) i.MX53 RM.

Best regards
igor
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[vsiles]

Great, thanks you. So basically when I read

static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
                               unsigned long parent_rate)
{
     struct clk_pllv3 *pll = to_clk_pllv3(hw);
     u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET);
     u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET);
     u32 div = readl_relaxed(pll->base) & pll->div_mask;

     return (parent_rate * div) + ((parent_rate / mfd) * mfn);
}
‍‍‍‍‍‍‍‍‍‍

on some Linux implementation, they just don't care about signedness and expect the frequency to be always positive.