Where CLK(input) come from ?

[ko-hey]

Hi all

I'm using i.MX6Solo and  have questions about uSDHC controller.

According to Figure 67-2 of RM, Async FIFO use a clock that selected from CLK(input) or CLK(output).

Where CLK(input) come from ?

And how can user select CLK(input) or CLK(output) ?

ko-hey

[Yuri · Accepted solution]

Hello,

Terms CLK, DATA[7:0], and CMD relate to SD interface. In this sense

the CLK(input) is not used on i.MX6 uSDHC. CLK(output) is SD clock,

please refer to section 67.4.5 (Clock Generator) of the RM how it is generated. 

  Also, the base clock is the peripheral clock  ipg_clk (from ipg_clk_root), mentioned
in Table 67-5 (uSDHC Clocks) of the RM.

Have a great day,
Yuri

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[ko-hey]

Yuri

Thanks.

ko-hey