What's the size of the cache line of i.MX6 quad Processor

[shijunzhao]

What's the size of the L2 cache line of i.MX6 quad Processor?  I'm using an i.MX 6Quad SabreD board, and I have to know its size of L2 cache line.

I know most ARM CPUs use 64B cache line, but I see from some website that  the cache line is 32B on i.mx6q. Which is right? Thanks.

Below is the link of my board:

i.MX 6Quad SABRE Development Board | NXP 

Best Regards,

Zhao

[shijunzhao]

Dear  igor,

Thanks for your reply. From the PL310 cache controller manual, I see that the cache line is 32B.

• Fixed line length of 32 bytes (eight words or 256 bits).

[igorpadykov]

Hi Zhao

i.MX6Q L2 cache controller is described in sect.12.3.3 PL310 L2 Cache configuration

i.MX 6Dual/6Quad Applications Processor Reference Manual

and its characteristics can be found in PL310 Cache Controller Technical Reference Manual

https://static.docs.arm.com/ddi0246/b/DDI0246B_l2cc_pl310_r1p0_trm.pdf 

Best regards
igor
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