What is the usage of DDR3 CLK 200ohm resister in parallel?
Is it the terminator?
Why is it near the CPU?but not near the DDR-RAM?
Why choose 200ohm?but not 100ohm?
A better example of DDR3 routing is actually shown on the i.MX 6 series boards (we made improvements):
On the i.MX 6 series, the 200 Ohm resistors on the DRAM_SDCLKn differential pairs are parallel termination resistors. Technically we are using a fly-by topology for the SDCLK traces. Even though the schematic shows them near the CPU, they are to be placed furthest away from the CPU, after being routed to intervening DDR3 ICs. Please see the Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors for full details.
>> Why were 200 Ohm resistors chosen?
Several DDR3 design guides recommend that two 100 Ohm termination resistors be used (Rn), connected together in series with a capacitor connected to the mid-point reference to the DRAM operating voltage:
We found it unnecessary to use the capacitor referenced to the DRAM operating voltage. We simply deleted the capacitor. Since there was no real reason to have two separate resistors, we combine the two 100 Ohm resistors into one 200 Ohm resistor. We have found this works well, and have made no further changes. If you wish to experiment with your own design, I would recommend going back to the two resistor and capacitor design and determine what values you like best.
Now going back to the i.MX53 design on the Quick Start board.
I am not sure where you got Figure 2-11 that you show in your first post. I have never seen it before. The picture you show is a point-to-point topology, so the caption is wrong. In this case, since a single resistor at the break-off point is used, a single 100 - 120 Ohm resistor is proper. This is a probably a mistake on the Quick Start schematics, but we are not going to change it at this point. Too many people are using 200 Ohms and it works fine. Also the statement in the Hardware User Guide for i.MX53 Quick Start Board is based on the initial schematic and should also be changed to 100 Ohms if and when we change the schematic.
The reality is that the 100 Ohm resistor should be placed right next to the split of the clock traces, so on the Quick Start board, not only should the resistor be 100 Ohms, but the traces should split before being routed under the DDR3 ICs.
Finally, in the last picture you show one clock line being split to four different ICs. It may be best for this design to use fly-by topology and use one parallel resistor at the end, but if you are going to use a point-to-point split for four ICs, I believe that you would place 400 - 480 Ohm resistors, one each next to the four DDR3 ICs. That would place four resistors in parallel on the clock traces so that the total resistance seen by the traces would be 100 - 120 Ohms. You would want to place the resistors as close to the DDR3 pins as possible, so you would probably not want to put a DDR3 directly underneath a second DDR3, but would most likely want all four DDR3 ICs on the same side of the PCB.
Cheers,
Mark
A better example of DDR3 routing is actually shown on the i.MX 6 series boards (we made improvements):
On the i.MX 6 series, the 200 Ohm resistors on the DRAM_SDCLKn differential pairs are parallel termination resistors. Technically we are using a fly-by topology for the SDCLK traces. Even though the schematic shows them near the CPU, they are to be placed furthest away from the CPU, after being routed to intervening DDR3 ICs. Please see the Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors for full details.
>> Why were 200 Ohm resistors chosen?
Several DDR3 design guides recommend that two 100 Ohm termination resistors be used (Rn), connected together in series with a capacitor connected to the mid-point reference to the DRAM operating voltage:
We found it unnecessary to use the capacitor referenced to the DRAM operating voltage. We simply deleted the capacitor. Since there was no real reason to have two separate resistors, we combine the two 100 Ohm resistors into one 200 Ohm resistor. We have found this works well, and have made no further changes. If you wish to experiment with your own design, I would recommend going back to the two resistor and capacitor design and determine what values you like best.
Now going back to the i.MX53 design on the Quick Start board.
I am not sure where you got Figure 2-11 that you show in your first post. I have never seen it before. The picture you show is a point-to-point topology, so the caption is wrong. In this case, since a single resistor at the break-off point is used, a single 100 - 120 Ohm resistor is proper. This is a probably a mistake on the Quick Start schematics, but we are not going to change it at this point. Too many people are using 200 Ohms and it works fine. Also the statement in the Hardware User Guide for i.MX53 Quick Start Board is based on the initial schematic and should also be changed to 100 Ohms if and when we change the schematic.
The reality is that the 100 Ohm resistor should be placed right next to the split of the clock traces, so on the Quick Start board, not only should the resistor be 100 Ohms, but the traces should split before being routed under the DDR3 ICs.
Finally, in the last picture you show one clock line being split to four different ICs. It may be best for this design to use fly-by topology and use one parallel resistor at the end, but if you are going to use a point-to-point split for four ICs, I believe that you would place 400 - 480 Ohm resistors, one each next to the four DDR3 ICs. That would place four resistors in parallel on the clock traces so that the total resistance seen by the traces would be 100 - 120 Ohms. You would want to place the resistors as close to the DDR3 pins as possible, so you would probably not want to put a DDR3 directly underneath a second DDR3, but would most likely want all four DDR3 ICs on the same side of the PCB.
Cheers,
Mark
Thank you for your answer.I just confused with the Quick Start board.Now I understand.
My design is just a Point-to-Point System.I think just a 100ohm resistor near to the DDR3 IC in parallel will be OK.
As was mentioned in "TN-46-14: Hardware Tips for Point-to-Point System Design Routing" by micron:
As stated in “Miscellaneous VTTDesign Guidelines” on page 6, place a differential termination resistor (RT) of 100–200Ω
between CK# and CK near the DDR component input pins.
Figures 9 and 10 show recommended DDR routing topology and RTplacement for two clock pairs.
• If the trace lengths from split point to DDR components are less than ~1in (2.5cm), use a single 100–120Ωresistor (RT) at the split point (Figure 9).
• If the lengths from the split point to the DRAM devices are greater than ~1in (2.5cm), use two resistors located near the respective DDR components (Figure 10). These resistors are in parallel, so each RTshould be 200–240Ωto keep the effective resistance at 100–120Ω.
What does this sentence mean?
According to micron's artical,I think it means to put four 200ohm resistor near all four DRAMs.
So,"i.MX53 System Development User’s Guide, Rev. 1" may be a mistake.
Am I right?
