What instruction sets the bit "PLL Lock Done" in PCIE PHY on I.MX8MM?

[jonifndef]

I'm working with the PCIE PHY driver for the IMX8MM platform. 

I'm reading a register called CMN_REG075 (address 0x32F0 0000 + 0x1D4) and need to know what instructions are needed for the 0 and 1 bits of that register to be set. From the IMX8MM reference manual:
bit 0 - PLL AFC Done
bit 1 - PLL Lock Done

Both these bits need to be set, but what other registers affect these bits?

I want to use the internal SOC PLL refclk. 

[Bio_TICFSL]

Hello,

In general PLL lock timeout can be caused by quality or reference clock

one can consider sect.3.9. PCIE connectivity i.MX 8M Mini Hardware Developer’s Guide

If for some reason a PLL goes open lock, then a whole clock tree within the SoC will change frequency. You might overclock or underclock subsystems, so you might face some unexpected crashes. If the SCU PLL itself loses lock and the MPU crashes, the SoC will be reset by the SC watchdog.

Regard