What can function clk_gate_endisable do?

[jiangzhifei]

Hi !

   In driver/clk/clk-gate.c file, the function clk_gate_endisable make sai2 mclk start output signal, Which register does this function operate?

best regards!

[igorpadykov]

Hi jiang

for i.MX6UL  MSEL always selects MCLK option 1(0b01) in hardware connection,
option 1 means SAx_CLK_ROOT.  So enabling sai and ungating clock with CCM_CCGR5

will make sai mclk start output signal.

Best regards
igor
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[jiangzhifei]

Hi igorpadykov

I add some print in clk_gate_endisable, it change the register value from 0x8010001e to 0x8010201e, and then sai2 mclk start output signal, I want to know which register has been changed?

Best regards

[jiangzhifei]

Hi igor!

I add print before and after clk_gate_endisable, but the value of CCM_CCGR5 is not change, and the signal change start on sai2 mclk, so there is another register make sai2 mclk start output...

[ 35.019058] get CCM_CCGR5 value = 0xf3ffc3ff
[ 35.023365] get CCM_CSCMR1 value = 0x4902840
[ 35.027667] get CCM_CS2CDR value = 0xdb6cf
[ 35.031794] get CCM_CCOSR value = 0xa0001
[ 35.035831] !!!!!!!!!!!!!!!!!!test able2 2
[ 35.039957] !!!!!!!!!!!!!!!!!!test able2 1
[ 35.044085] get CCM_CCGR5 value = 0xf3ffc3ff
[ 35.048386] get CCM_CSCMR1 value = 0x4902840
[ 35.052686] get CCM_CS2CDR value = 0xdb6cf
[ 35.056813] get CCM_CCOSR value = 0xa0001