So, per that presentation, I should not be having a problem. I am running the VPU at 352Mhz, I am running 6 streams at 30fps, 640x480 resolution. There should be ample headroom.. My encoder parameters are: "gop_size": 0, "bit_rate": 1250, "quant": 23. Horz = 640, Vert = 480, fps = 30. Everything else is default.
Interesting note: I've been tinkering with the MMDC arbitration priorities for VPU, IPU and PCIe (where our video frames come in). I set their priorities as follows:
# first set PCIe write priority so that TW6869 can get its data to RAM. Highest Priority
devmem 0xC4A104 32 0x0000000F
# next set VPU write priorities. Third Highest Priority
devmem 0xC49104 32 0x00000006
devmem 0x844104 32 0x00000006
# finally set IPU1 & IPU2. Second Highest Priority.
devmem 0x20e0018 32 0x77777777
devmem 0x20e001C 32 0x77777777
I've left the default read priorities as default (2) for VPU and PCIe. Changing the read priorities to make write make the failure occur more frequently. Setting all priorities equal causes the problem to occur more frequently.
My memory bus load is at 82%