VDD_SNVS_IN Connection in SABRE Reference Design

[ko-hey]

Hi all

I want to know the reason why VDD_SNVS_IN connects VSNVS_3V0 and VGEN5_2V8 in SABRE-SDB.

According to the P2 of SDB's schematic, VDD_SNVS_IN  connects both VSNVS_3V0 and VGEN5_2V8 as below.

I think VSNVS_3V0 is enough to operate VDD_SNVS_IN.

Why does the VDD_SNVS_IN connect both VSNVS_3V0 and VGEN5_2V8 ?

Ko-hey

[alfred_liu · Accepted solution]

Hi, Ko-hey

this is to ensure the volatge of VDD_SNVS doesn't not drop too low.

the reference schematic is for early TO chips, when powering up, some chips may consume current up to 1mA on SNVS_IN , which exceeds the output capacitor of Pfuse100 (400uA).

latest TO has fixed the issue, we didn't see the voltage drop on customer's boards till now.

you can remove the diode on your board, or you can remain it and DNP it by default.

[ko-hey]

Hi Weisong Liu

So we need to connect only VSNVS_3V0.

Is it correct ?

Ko-hey

[alfred_liu]

Hi, ko-hey​

yes, you are correct.

make your customer is using the latest TO chips.

in addition, you need to care about the other circuits which are connected to SNVS_IN.

here is the notes in our datesheet:

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2 Under normal operating conditions, the maximum current on VDD_SNVS_IN is shown Table 8. The maximum VDD_SNVS_IN

current may be higher depending on specific operating configurations, such as BOOT_MODE[1:0] not equal to 00, or use of

the Tamper feature. During initial power on, VDD_SNVS_IN can draw up to 1 mA if the supply is capable of sourcing that

current. If less than 1 mA is available, the VDD_SNVS_CAP charge time will increase.

=========================================

[ko-hey]

Hi Weisong Liu

Let me confirm one more thing.

The TO chips that you mentioned is i.MX6.

Is it correct ?

Ko-hey

[alfred_liu]

Hi, ko-hey​

yes, sure for imx6.