Hi everyone,
I have a project running on a 1064 that will be using multiple timers, specifically the Quad Timer (TMR) and the Periodic Interrupt Timer (PIT). No matter what I try, I cannot keep these two timers in sync relative to each other, the PIT starts to lead the TMR after 10-30s depending on the clock configurations, and the lead is additive over time. What I have tried so far:
Set both the IPGCLK (TMR clock) and PERCLK (PIT clock) to 50MHz, PERCLK is derived from IPG
Set both compare registers in TMR and PIT to 50,000, which is a 1ms tick
Minimize ISR as much as possible, ISR went from what we need in our application to literally {clear status flags; ++time_ms; SDK_ISR_EXIT_BARRIER;} for both PIT and TMR.
Set both interrupts to NVIC Priority 10 (10 is an arbitrary priority, what is important is they have the same priority.)
Is it possible to have these timers tick at the same rate (or some clock multiple of each other) and not drift apart from each other over time, or is there some hardware detail I am missing that makes it impossible to have these timers in sync?