i.MX.RT 1050 - XBAR and Quad timer input capture function - interrupt is not triggered

[Cindy]

I modified the qtmr input capture example so that I can feed PWM signal to pin-GPIO_AD_B0_09. I am trying to connect this input to a qtmr using Xbar. The PWM freq is 2KHz and duty cycle is 50%. However, the interrupt is not happening. Could you please tell me what is missing from the code?

#include "fsl_debug_console.h"
#include "pin_mux.h"
#include "clock_config.h"
#include "board.h"
#include "fsl_qtmr.h"
#include "fsl_iomuxc.h"
#include "fsl_xbara.h"

#define BOARD_QTMR_BASEADDR TMR1
#define BOARD_QTMR_INPUT_CAPTURE_CHANNEL kQTMR_Channel_0
#define QTMR_CounterInputPin kQTMR_Counter0InputPin

#define QTMR_IRQ_ID TMR1_IRQn
#define QTMR_IRQ_HANDLER TMR1_IRQHandler

volatile bool qtmrIsrFlag = false;

void QTMR_IRQ_HANDLER(void)
{
/* Clear interrupt flag.*/
QTMR_ClearStatusFlags(BOARD_QTMR_BASEADDR, BOARD_QTMR_INPUT_CAPTURE_CHANNEL, kQTMR_EdgeFlag);

qtmrIsrFlag = 1;
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
exception return operation might vector to incorrect interrupt */
__DSB();
}

int main(void){

BOARD_ConfigMPU();
BOARD_InitBootPins();
BOARD_InitBootClocks();
BOARD_InitDebugConsole();

IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_XBAR1_IN21, 1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_XBAR1_IN21, 0x10B0U);

XBARA_Init(XBARA1);
XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputIomuxXbarIn21, kXBARA1_OutputQtimer1Tmr0Input);

QTMR_GetDefaultConfig(&qtmrConfig);

/* Initial the input channel. */
qtmrConfig.primarySource = kQTMR_ClockDivide_16; //QTMR_PRIMARY_SOURCE;
QTMR_Init(BOARD_QTMR_BASEADDR, BOARD_QTMR_INPUT_CAPTURE_CHANNEL, &qtmrConfig);

/* Setup the input capture */
QTMR_SetupInputCapture(BOARD_QTMR_BASEADDR, BOARD_QTMR_INPUT_CAPTURE_CHANNEL, QTMR_CounterInputPin, false, true,
kQTMR_RisingEdge);

/* Enable at the NVIC */
EnableIRQ(QTMR_IRQ_ID);

/* Enable timer compare interrupt */
QTMR_EnableInterrupts(BOARD_QTMR_BASEADDR, BOARD_QTMR_INPUT_CAPTURE_CHANNEL, kQTMR_EdgeInterruptEnable);

/* Start the input channel to count on rising edge of the primary source clock */
QTMR_StartTimer(BOARD_QTMR_BASEADDR, BOARD_QTMR_INPUT_CAPTURE_CHANNEL, kQTMR_PriSrcRiseEdge);

while (1)
{
while (!qtmrIsrFlag)
{

}

qtmrIsrFlag = 0;
PRINTF("\r\n****qtmr interrupt detected.****\n");
}

}

Thanks!

Best Regards,

Cindy

[jeremyzhou · Accepted solution]

Hi,
Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
After having a brief review of the code, I find you miss to configuring the QTIMER1_TRM0_INPUT_SEL in the IOMUXC_GPR_GPR6 register to enable QTIMER1 TMR0 from XBAR.
Please fix it and give it a try again.
Hope it helps.
Have a great day,
TIC

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[Cindy]

Dear jeremyzhou,

You have provided an accurate solution to my problem and

allow me to make further progress. The problem has been fixed.

I appreciate your prompt reply very much.

Thank you!

Yours Sincerely,

Cindy