Hi, I am using IMX8MN cortex-M7 with SDK 2.16.000. When using UART1 with SDMA in IDLE detection mode, when there is full duplex transfer (TX and RX at the same time), when the SDMA RX callback is called, the beginning of the TX buffer is overwritten (most of the times it is the first byte, but sometimes it is even more than the first byte).
The IDLE condition is set to 4 frames (the shortest period). If the RX received N bytes, the N+1 byte of the RX buffer is overwritten with a value that was not received (I do not know from where), and the same value is written to the beginning of the TX buffer also.
For example, if UART RX received 30 bytes, the 31st byte of the RX buffer is overwritten with a dummy byte, but also the 1st byte of the TX buffer. It happens only for the TX when TX is sent at the same time that RX is done also.
My configuration of the SDMA is as follow:
What can be the reason for this, and how it can be resolved?
Hi Okobelnc:
Hi Daniel.
Yes, I am using FreeRTOS. Here are the registers USR1 and USR2 of UART1 values:
Hi @okobelnc
According to ERR050362 in https://www.nxp.com/docs/en/errata/IMX8MN_0N14Y.pdf , AXI bus may experience error when dealing with unaligned burst writes.
You may try 64-bit aligned data (e.g. 32 bytes) and see if the issue is gone. If so, make your buffer 64-bit aligned and leave margin between buffers to mitigate the impact.
Regards
Daniel