Hi, I am using IMX8MN cortex-M7 with SDK 2.16.000. When using UART1 with SDMA in IDLE detection mode, when there is full duplex transfer (TX and RX at the same time), when the SDMA RX callback is called, the beginning of the TX buffer is overwritten (most of the times it is the first byte, but sometimes it is even more than the first byte).
The IDLE condition is set to 4 frames (the shortest period). If the RX received N bytes, the N+1 byte of the RX buffer is overwritten with a value that was not received (I do not know from where), and the same value is written to the beginning of the TX buffer also.
For example, if UART RX received 30 bytes, the 31st byte of the RX buffer is overwritten with a dummy byte, but also the 1st byte of the TX buffer. It happens only for the TX when TX is sent at the same time that RX is done also.
My configuration of the SDMA is as follow:
- UART1 TX channel is 6.
- UART1 RX channel is 5.
- UART1 TX channel priority is 4
- UART1 RX channel priority is 5.
- UART1 TX FIFO watermark is 2.
- UART1 RX FIFO watermark is 1.
- UART1 RTS watermark is 16 (half of the RX FIFO size).
- RX buffer size is 4120 bytes (aligned to 4), while every RX transaction is up to 3090 bytes (actually most of the RX transactions are around ~30 bytes). The same RX buffer is used for every RX transaction (the transactions start from the same memory address).
- TX buffer size is up to 4124 bytes (aligned to 256), while every TX transaction is up to 3093 bytes (actually most of the TX transactions are around ~300 bytes). The same TX buffer is used for every TX transaction (the transactions start from the same memory address). The TX buffer starts with 0xBD byte, and I see that in those scenarios, the 0xBD is replaced by the N+1 byte in the RX buffer.
What can be the reason for this, and how it can be resolved?
