U-boot and Mfg tool code changes for change in DDR3 from 512MB to 256 MB

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U-boot and Mfg tool code changes for change in DDR3 from 512MB to 256 MB

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jayebc
Contributor II

Hi All,

>> In  imx6ull evalution board we want to change DDR3 from 512MB(MT41K512M16HA) to 256MB(MT41K256M16TW).  So I want to know the changes need to done in the Uboot.

>> Also want to know any changes has to be done in the Mfg tool to flash U-boot, Kernel, dtb, and rootfs.

Appreciate any help or advice you could give me.  Awaiting for your response.

Thank you,
Jayalaxmi

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igorpadykov
NXP Employee
NXP Employee

Hi jaya

one can look at mfg tool presentation

AMF-AUT-T2324 - Manufacturing Tool 

For new board it is necessary to run ddr test

i.MX6/7 DDR Stress Test Tool V2.90 

and rebuild mfg tool firmware (changing files in /firmware folder) with new

calibration settings (found from ddr test), place them in uboot board file

uboot/board/freescale/mx6ullevk/imximage.cfg

uboot-imx.git - Freescale i.MX u-boot Tree 

change ddr size, #define PHYS_SDRAM_* in uboot/include/configs/mx6ullevk.h

For rebuilding use sect.6.2 Manufacturing Tool, MFGTool attached Yocto Guide

attached Yocto Guide.

Best regards
igor
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jayebc
Contributor II

!Hi Igor 

Thanks for response. I am running  ddr stress tool from u-boot command line for imx6ull evk(512mb DDR). After some steps it is asking 

"Enter as a 4-digit HEX value, example 0004, then hit enter " ,

I am not sure what I need to enter here.

Could you please tell me how to proceed next.

I have given below the  stress test logs.

---------------------------------------------------------------

Hit any key to stop autoboot: 0
=>
=>
=>
=> dcache off
=> icache off
=> fatload mmc 1:1 0x00907000 ddr-test-uboot-jtag-mx6ull.bin
reading ddr-test-uboot-jtag-mx6ull.bin
66368 bytes read in 26 ms (2.4 MiB/s)
=> go 0x00907000
## Starting application at 0x00907000 ...

============================================
DDR Stress Test (2.9.0)
Build: Jul 6 2018, 15:24:04
NXP Semiconductors.
============================================

============================================
Chip ID
CHIP ID = i.MX6 UltraLiteLite(0x65)
(0x65)
Internal Revision = TO1.0
============================================

============================================
Boot Configuration
SRC_SBMR1(0x020d8004) = 0x00000812
SRC_SBMR2(0x020d801c) = 0x02000001
============================================

What ARM core speed would you like to run?
Type 1 for 200MHz, 2 for 400MHz, 3 for 528MHz, 4 for 700MHz
ARM Clock set to 400MHz

============================================
DDR configuration
DDR type is DDR3
Data width: 16, bank num: 8
Row size: 15, col size: 10
Chip select CSD0 is used
Density per chip select: 512MB
============================================

Current Temperature: 41
============================================

Please select the DDR density per chip select (in bytes) on the board
Type 0 for 2GB; 1 for 1GB; 2 for 512MB; 3 for 256MB; 4 for 128MB; 5 for 64MB; 6 for 32MB
DDR density selected (MB): 256


Would do you want to change VDD_SOC_CAP/VDD_ARM_CAP voltage? Type 'y' to run and 'n' to skip

Please select VDD_SOC_CAP volatage on the board
Type 0 for 1.15V; 1 for 1.175V; 2 for 1.2V; 3 for 1.225V; 4 for 1.25V; 5 for 1.275V; 6 for 1.3V
VDD_SOC_CAP option: 0

Please select VDD_ARM_CAP volatage on the board
Type 0 for 1.15V; 1 for 1.175V; 2 for 1.2V; 3 for 1.225V; 4 for 1.25V; 5 for 1.275V; 6 for 1.3V
VDD_ARM_CAP option: 0


Would do you want run DDR Calibration? Type 'y' to run and 'n' to skip

Calibration will run at DDR frequency 400MHz. Type 'y' to continue.
If you want to run at other DDR frequency. Type 'n'
Please enter the MR1 value on the initilization script
This will be re-programmed into MR1 after write leveling calibration
Enter as a 4-digit HEX value, example 0004, then hit enter

--------------------------------------------------------------------------------------------------------

As I am struck with this could you please help me.

Thanks in advance,

Jaya

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igorpadykov
NXP Employee
NXP Employee

Hi Jaya

MR1 default value 4 will be fine for test.

Best regards
igor

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jayebc
Contributor II

Thank you Igor.

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