Hello!
We are use UART2 on our board, follow my configuration for U-Boot.
#define CONFIG_MXC_UART
#define CONFIG_UART_BASE_ADDR UART2_BASE_ADDR
#define CONFIG_BAUDRATE | 115200 |
#define CONFIG_SYS_BAUDRATE_TABLE | {9600, 19200, 38400, 57600, 115200} |
#define CONFIG_EXTRA_ENV_SETTINGS | \ | |
"bootargs_base=setenv bootargs console=ttymxc1,115200\0"\ | ||
"bootargs_nand=setenv bootargs ${bootargs} ip=off " \ | ||
"root=/dev/mtdblock4 rootfstype=jffs2\0" \ | ||
"bootcmd_nand=run bootargs_base bootargs_nand; " \ | ||
"nboot 0x80700000 0 0x1080000; bootm\0" \ | ||
"bootargs_mmc=setenv bootargs ${bootargs} ip=off " | \ | |
"root=/dev/mmcblk0p1 rootwait rw\0" | \ | |
"bootcmd_mmc=run bootargs_base bootargs_mmc; " | \ | |
"mmc dev 0; " | \ | |
"mmc read ${loadaddr} 0x800 0x1800; bootm\0" | \ | |
"bootcmd=run bootcmd_mmc\0" |
static void setup_uart(void)
{
u32 cfg = (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
PAD_CTL_PUE_PULL | PAD_CTL_100K_PU |
PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH);
/* UART2 RXD */
mxc_request_iomux(MX53_PIN_EIM_D27, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX53_PIN_EIM_D27, cfg);
mxc_iomux_set_input(MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
INPUT_CTL_PATH1);
/* UART2 TXD */
mxc_request_iomux(MX53_PIN_EIM_D26, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX53_PIN_EIM_D26, cfg);
}
Unfortunally I not get any U-Boot output if it started from NAND or SD, but I get U-Boot output and can work with it if I load it via MfgTool.
How should I configure uart for work with U-Boot?
Thank you and excuse me my bad english.
Solved! Go to Solution.
Ok, problem in Linux solved, in my case arch/arm/plat-mxc/include/mach/iomux-mx53.h have incorrect parameters for _MX53_PAD_EIM_D26__UART2_TXD_MUX, please see attache.
Hello,Kirill,
From your description, u-boot in OS Firmware can normally work in memory,and startup messages can output to console when MFG Tool is burning images.So your configuration for UART2 in u-boot is correct.
After burning images, when you normally boot system form SD card, you can't see startup messages on console, I judge ROM code didn't normally read u-boot code into iRAM or read unexpected code.
So I think you should check u-boot, the issue should be from u-boot. Could you tell me which BSP version you are using ?
Regards,
Weidong
Hello, Weidong!
How can I check U-Boot, what parameters should I recheck?
Now I work with U-Boot 2009.08 and Linux-2.6.35.3 form L2.6.35_11.09.01_ER_source_bundle.tar.gz
>
Hello,Kirill,
Wait, Let us confirm boot mode setting on your board at first, Assume you boot from eSDHC3 port with SD card.
(1)BOOT_MODE0=0 & BOOT_MODE1=1
(2)EIM PADs setting
EIM_A20 = 1
EIM_A19 = 0
EIM_A18 = 1
EIM_EB0 = 0
EIM_EB1 = 1
EIM_DA0 = 0
---------------------
EIM_DA6/EIM_A21/EIM_LBA/EIM_DA1/EIMDA2 = 1
--------------------
EIM_A22/EIM_A16/EIM_DA7/EIM_DA8 = 0
Then how about your settings ? The boot settings can also cause boot failure !
Regards,
Weidong
Hello, Weidong!
I use eSDHC1 for booting.
My configuration for booting from SD:
#define CONFIG_CMD_MMC
#ifdef CONFIG_CMD_MMC
#define CONFIG_MMC 1
#define CONFIG_GENERIC_MMC
#define CONFIG_IMX_MMC
#define CONFIG_SYS_FSL_ESDHC_NUM 1
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_DOS_PARTITION 1
#define CONFIG_CMD_FAT 1
#define CONFIG_CMD_EXT2 1
/* detect whether ESDHC1 or ESDHC3 is boot device */
#define CONFIG_DYNAMIC_MMC_DEVNO
#define CONFIG_EMMC_DDR_PORT_DETECT
#define CONFIG_EMMC_DDR_MODE
/* port 1 (ESDHC3) is 8 bit */
#define CONFIG_MMC_8BIT_PORTS 0x2
#endif
#ifdef CONFIG_CMD_MMC
struct fsl_esdhc_cfg esdhc_cfg[2] = {
{MMC_SDHC1_BASE_ADDR, 1, 1},
{MMC_SDHC3_BASE_ADDR, 1, 1},
};
#ifdef CONFIG_DYNAMIC_MMC_DEVNO
int get_mmc_env_devno(void)
{
uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
return (soc_sbmr & 0x00300000) ? 1 : 0;
}
#endif
#ifdef CONFIG_EMMC_DDR_PORT_DETECT
int detect_mmc_emmc_ddr_port(struct fsl_esdhc_cfg *cfg)
{
return (MMC_SDHC3_BASE_ADDR == cfg->esdhc_base) ? 1 : 0;
}
#endif
int esdhc_gpio_init(bd_t *bis)
{
s32 status = 0;
u32 index = 0;
u32 cfg = (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
PAD_CTL_PUE_PULL | PAD_CTL_ODE_OPENDRAIN_NONE |
PAD_CTL_DRV_HIGH);
for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; ++index) {
switch (index) {
case 0:
#if 0
/*
our board haven't this pins
with this configuration boot from SD-card success
*/
/* ESDHC1 CD */
mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT6);
mxc_iomux_set_pad(MX53_PIN_GPIO_1,
cfg | PAD_CTL_360K_PD);
/* ESDHC1 WP */
mxc_request_iomux(MX53_PIN_DI0_PIN4, IOMUX_CONFIG_ALT3);
mxc_iomux_set_pad(MX53_PIN_DI0_PIN4,
cfg | PAD_CTL_360K_PD |
PAD_CTL_SRE_FAST);
#endif
/* ESDHC1 CLK */
mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
cfg | PAD_CTL_100K_PU);
/* ESDHC1 CMD */
mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
cfg | PAD_CTL_100K_PU);
/* ESDHC1 DAT0 */
mxc_request_iomux(MX53_PIN_SD1_DATA0,
IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
cfg | PAD_CTL_100K_PU);
/* ESDHC1 DAT1 */
mxc_request_iomux(MX53_PIN_SD1_DATA1,
IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
cfg | PAD_CTL_100K_PU);
/* ESDHC1 DAT2 */
mxc_request_iomux(MX53_PIN_SD1_DATA2,
IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
cfg | PAD_CTL_100K_PU);
/* ESDHC1 DAT3 */
mxc_request_iomux(MX53_PIN_SD1_DATA3,
IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
cfg | PAD_CTL_100K_PU);
/* ESDHC1 LCTL */
mxc_request_iomux(MX53_PIN_GPIO_18, IOMUX_CONFIG_ALT6);
mxc_iomux_set_pad(MX53_PIN_GPIO_18,
cfg | PAD_CTL_360K_PD);
break;
default:
printf("Warning: you configured more ESDHC controller"
"(%d) as supported by the board(2)\n",
CONFIG_SYS_FSL_ESDHC_NUM);
return status;
}
status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
}
return status;
}
int board_mmc_init(bd_t *bis)
{
if (!esdhc_gpio_init(bis))
return 0;
else
return -1;
}
#endif
And configuration for booting from NAND:
#define CONFIG_CMD_NAND
#if defined(CONFIG_CMD_NAND)
#define CONFIG_MXC_NAND
#define CONFIG_SYS_NAND_MAX_CHIPS 8
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_NAND_FW_16BIT 1 /* 1: 16bit 0: 8bit */
#define CONFIG_CMD_FLASH
#endif
#if defined(CONFIG_MXC_NAND)
void setup_nand(void)
{
u32 cfg = (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
PAD_CTL_DRV_HIGH);
clk_config(0, 34, NFC_CLK);
/* EMI NAND_WEIM_DA[0] */
mxc_request_iomux(MX53_PIN_EIM_DA0, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_DA0, cfg);
/* EMI NAND_WEIM_DA[1] */
mxc_request_iomux(MX53_PIN_EIM_DA1, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_DA1, cfg);
/* EMI NAND_WEIM_DA[2] */
mxc_request_iomux(MX53_PIN_EIM_DA2, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_DA2, cfg);
/* EMI NAND_WEIM_DA[3] */
mxc_request_iomux(MX53_PIN_EIM_DA3, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_DA3, cfg);
/* EMI NAND_WEIM_DA[4] */
mxc_request_iomux(MX53_PIN_EIM_DA4, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_DA4, cfg);
/* EMI NAND_WEIM_DA[5] */
mxc_request_iomux(MX53_PIN_EIM_DA5, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_DA5, cfg);
/* EMI NAND_WEIM_DA[6] */
mxc_request_iomux(MX53_PIN_EIM_DA6, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_DA6, cfg);
/* EMI NAND_WEIM_DA[7] */
mxc_request_iomux(MX53_PIN_EIM_DA7, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_DA7, cfg);
/* EMI NAND_WEIM_DA[8] */
mxc_request_iomux(MX53_PIN_EIM_DA8, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_DA8, cfg);
/* EMI NAND_WEIM_DA[9] */
mxc_request_iomux(MX53_PIN_EIM_DA9, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_DA9, cfg);
/* EMI NAND_WEIM_DA[10] */
mxc_request_iomux(MX53_PIN_EIM_DA10, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_DA10, cfg);
/* EMI NAND_WEIM_DA[11] */
mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_DA11, cfg);
/* EMI NAND_WEIM_DA[12] */
mxc_request_iomux(MX53_PIN_EIM_DA12, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_DA12, cfg);
/* EMI NAND_WEIM_DA[13] */
mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_DA13, cfg);
/* EMI NAND_WEIM_DA[14] */
mxc_request_iomux(MX53_PIN_EIM_DA14, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_DA14, cfg);
/* EMI NAND_WEIM_DA[15] */
mxc_request_iomux(MX53_PIN_EIM_DA15, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_DA15, cfg);
/* EMI NANDF_ALE */
mxc_request_iomux(MX53_PIN_NANDF_ALE, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_NANDF_ALE, cfg | PAD_CTL_HYS_ENABLE);
/* EMI NANDF_CLE */
mxc_request_iomux(MX53_PIN_NANDF_CLE, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_NANDF_CLE, cfg | PAD_CTL_HYS_ENABLE);
/* EMI NANDF_CS[0] */
mxc_request_iomux(MX53_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_NANDF_CS0, cfg | PAD_CTL_HYS_ENABLE);
/* EMI NANDF_RB[0] */
mxc_request_iomux(MX53_PIN_NANDF_RB0, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_NANDF_RB0, cfg | PAD_CTL_HYS_ENABLE);
/* EMI NANDF_RB_B */
mxc_request_iomux(MX53_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_NANDF_RE_B, cfg | PAD_CTL_HYS_ENABLE);
/* EMI NANDF_WE_B */
mxc_request_iomux(MX53_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_NANDF_WE_B, cfg | PAD_CTL_HYS_ENABLE);
/* EMI NANDF_WP_B */
mxc_request_iomux(MX53_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_NANDF_WP_B, cfg | PAD_CTL_HYS_ENABLE);
}
void setup_nfc(void)
{
volatile unsigned int reg = 0;
reg = readl(NFC_BASE_ADDR + 0x24);
reg &= ~(0x3 << 0);
reg |= (0x1 << 0);
writel(reg, NFC_BASE_ADDR + 0x24);
reg = readl(NFC_BASE_ADDR + 0x28);
reg &= ~((0x7 << 12) | (0x1 << 3));
writel(reg, NFC_BASE_ADDR + 0x28);
}
#endif
Sorry for big post.
>
Hello,Kirill ,
I noticed your note on above " with this configuration boot from SD-card success" , what does it mean ?
Does it mean you can boot the board from SD1 port successfully ?
Regards,
Weidong
Hello, Weidong!
Yes, system successfully run from SD1, but UART output not work, as I write early.
>
Hello,Kirill,
Please try it in hearder file :
#define CONFIG_MXC_UART 2
Regards,
Weidong
Hello, Weidong!
I try late, now I havn't hardware, but I think what this is not solve problem because macros CONFIG_MXC_UART only enabled building serial_mxc.
Thank you for your answer, jimmychan!
But I haven't problem in Linux, only in U-Boot and after loading Linux...
U-Boot - I can't get any output after loading from NAND or SD, after loading via MFGToll all ok.
After loading Linux I can't put any commands, but system configured on work with UART2 and I get output from programms, follow my inittab:
::sysinit:/etc/init.d/rcS
::respawn:/sbin/getty -L ttymxc1 115200
::restart:/sbin/init
::ctrlaltdel:/bin/umount -a -r
>
In your U-boot, please try to set CONFIG_CONS_INDEX to 2 .
Have you set the uart_clk and early_console_setup in kernel?
For your reference, https://community.freescale.com/message/311767#311767
Hello, jimmychan!
I try set CONFIG_CONS_INDEX, but this is not solve problem because this define not used in result binary.
As I write early I not have problem with output from Linux.
>