Timing for Boot mode configuration pins

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Timing for Boot mode configuration pins

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borisberman
Contributor III

Hello,

In our new project with iMX8, part of the boot mode configuration pins (BOOT_MODE0/1, SAI1_TXD1, SAI1_TXD4, and SAI1_TXD5) will be changed during active reset (I mean when POR_B input us low), but before rising edge of the POR_B it's will get the necessary value.

According to reference manual of iMX8 for BOOT_MODE0 and BOOT_MODE1, it's OK

Paragraph "6.1.2.1 Boot mode pin settings": The BOOT_MODE is initialized by sampling the BOOT_MODE0 and BOOT_MODE1 inputs on the rising edge of the POR_B.

Is this rule valid for other boot configuration pins also?

Thank You,

Boris

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igorpadykov
NXP Employee
NXP Employee

Hi Boris

for other pins it is not the same, sect.6.5.6.1.2.1 POR (SRC_POR_B)

i.MX8MDQ Reference Manual describes timings which enables OCOTP_CTRL and fusebox,

they later are used for sampling boot configuration and reading from fuses.


https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf

Best regards
igor
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borisberman
Contributor III

Hi Igor,

Thank You for your fast answer!

From sect.6.5.6.1.2. of i.MX8MDQ Reference Manual i understood that OCOTP_CTRL and fusebox clocks will be enabled after more than 2 XTALI clocks since reset signal (In my case POR_B pin) de-assertion.

Is this true conclusion?

Thank you

Boris

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igorpadykov
NXP Employee
NXP Employee

Hi Boris

yes true, also it will take some time for locking plls, prepare system clocks are read fuses.

from sect.6.5.6.1.2.2 COLD RESET:

Once the reset source deasserts, system_early_rst_b reset is deasserted after at least 2
XTALI clocks. The system_early_rst_b is used for the CCM and PLL-IPs to start
generating PLL clock outputs and the system root clocks.
Once the system root clocks are ready, the CCM will assert system_clk_ready signal.
This signal is generated during the start sequence in the CCM and it involves the
preparation of the PLLs to generate clock roots for functional operation.

from sect.6.5.6.3.1 BOOT_MODE Pin Latching:

The value of the BOOT_MODE pins will be latched after the OCOTP_CTRL asserts the
fuse read completion flag. After latching, the values of the BOOT_MODE pins are used
to determine the booting options of the core as described in the SRC_SBMRx registers.
The boot mode general purpose bits can be provided to the SRC from either e-fuses or
GPIO signals. The gpio_bt_sel e-fuse defines the source to be used to derive the boot
information. When gpio_bt_sel is set, e-fuses are used. When cleared, GPIO signals are
used.

Best regards
igor

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