The i.RAM(OCRAM) effective use way

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The i.RAM(OCRAM) effective use way

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george
Senior Contributor I

Dear all,

I develops the product which used i.MX6.

I want to use original RTOS, without using linux.

And I use iRAM (OCRAM) for operation speed-up.

Please tell me the way for speed-up of iRAM and CPU-core.

a)  Please tell me the iRAM clock speed change method.

b)  Please let me know the care point.

c)  Is there any idea for speed-up?

d)  Is there any document relevant to them?

Best Regards,

George

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AnsonHuang
NXP Employee
NXP Employee

Hi, George

     I looked into the CCM of i.MX6Q, the OCRAM's clock parent is AHB, and AHB is 133MHz when kernel boot up and AHB is system's clock, its max freq is 133MHz according to RM table 18-3. So as far as I know, we should NOT increase OCRAM's clk freq. But I do see there is write/read pipeline function in OCRAM chapter which might impact the delay of data read/write, it is controlled by IOMUX_GPR3[24:21], you can look through the RM chapter of OCRAM and IOMUX_GPR for details.

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bk300
Contributor I

I was curious if there was any further information on the OCRAM's speed?

I'm currently using an iMX6Q and am attempting to use the OCRAM as a shared memory between threads.  I wrote a quick test that looks similar to the following psuedo code...

Set GPIO pin HIGH

// Loop 1 million times

for( x = 0; x < 1000000; x++ )

{

     *(0x00900000) = x;  // Write to OCRAM

    y = *(0x00900000);   // Read from OCRAM

}

Set GPIO pin LOW

I monitored the GPIO pin using an oscope and the delay measured to be about 1 second.  At 1 million loops, the delay for a read/write pair to the OCRAM is about 1 microsecond...which seems really slow.  I've already disabled the read/write delays by clearing the IOMUX_GPR3[24:21] bits, so I'm not sure what else I can do.  Does anybody have some sort of explanation why the OCRAM appears to be so slow?

Thanks

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Yuri
NXP TechSupport
NXP TechSupport

Was instruction cache enabled ?

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AnsonHuang
NXP Employee
NXP Employee

Hi, George

     I looked into the CCM of i.MX6Q, the OCRAM's clock parent is AHB, and AHB is 133MHz when kernel boot up and AHB is system's clock, its max freq is 133MHz according to RM table 18-3. So as far as I know, we should NOT increase OCRAM's clk freq. But I do see there is write/read pipeline function in OCRAM chapter which might impact the delay of data read/write, it is controlled by IOMUX_GPR3[24:21], you can look through the RM chapter of OCRAM and IOMUX_GPR for details.

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george
Senior Contributor I

Dear Yongcai,

Thank you for the reply.

Helpful very much.

BR,

George

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