TLV320AIC3256 and MX6DL on Linux 4.9 kernel question

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TLV320AIC3256 and MX6DL on Linux 4.9 kernel question

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GregT
Contributor III

Hello,

I'm converting an audio driver composed of two modules from linux 3.0 to the latest linux 4.9 for the MX6 and having some difficulties.  Attached are the two versions of the file.  The first three are the linux 3.0 and the second three are for the linux 4.9.  The codec is a TLV320aic3256 connected to an MX6DL. I tried to minimize the differences and the 4.9 does compile and I can insmod it and have it recognize and initialize the TLV320AIC3256 but get no audio when running aplay.  One of the main issues I'm trying to resolve is how to enable the SSI2 using the device tree that was done in a board file on the linux 3.0 kernel.  I noticed in the CCGR 0x20c470c that the SSI2 clock was not enabled. The  board file has some code below.  Below that are my device tree entries.  Has anyone converted a board file into a device tree for the MX6DL SSI?

static struct imx_ssi_platform_data mx6_gpb_ssi_pdata = {
.flags = IMX_SSI_DMA | IMX_SSI_SYN,
};

static struct mxc_audio_platform_data mx6_gpb_audio_data = {
.ssi_num = 1,
.src_port = 2,
.ext_port = 6,
.init = mx6_gpb_aic3256_init,
.hp_gpio = -1,
};

mxc_register_device(&mx6_gpb_audio_device, &mx6_gpb_audio_data);

imx6q_add_imx_ssi(0, &mx6_gpb_ssi_pdata);

ssi2_clk = clk_get_sys("imx-ssi.1", NULL); // ssi2 is imx-ssi.1 (confusing huh)
if (IS_ERR(ssi2_clk)) {
pr_err("Error can't get ssi2_clk clock imx-ssi.1\n");
}

//// DEVICE TREE ENTRIES 

pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0
MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0
MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x120b0
MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0
MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x130b0
>;
};

sound {
compatible = "fsl,imx-audio-tlv320aic3256";
model = "tlv320aic3256";
cpu-dai = <&ssi2>;
ssi-controller = <&ssi2>;
sysclk = <4096000>;
audio-codec = <&tlv320aic3256>;
mux-int-port = <2>;
mux-ext-port = <6>;
};

soundmux {
compatible = "fsl,imx-audio-tlv320aic3256", "fsl,imx31-audmux";
reg = <0x021d8000 0x4000>;
};

tlv320aic3256: codec@18 {
compatible = "ti,aic3256";
reg = <0x18>;
ldoin-supply = <&reg_3p3v>;
iov-supply = <&reg_3p3v>;
sysclk = <4096000>;
clocks = <&clks 201>;
clock-names = "mclk";
resetn-gpio = GP_AUDIO_EN;
};

&ssi2 {
fsl,mode = "i2s-slave";
codec-handle = <&tlv320aic3256>;
status = "okay";
};

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi GregT

seems TLV320 codec is supported on phyFLEX boards

phyFLEX-i.MX 6 - Develop.phytec - PHYTEC Wiki 

[v2,2/4] ARM: dts: pbab01: enable I2S audio on phyFLEX-i.MX6 boards - Patchwork 

and one can look at its linux 4.9 releases

linux-mainline - linux kernel used by Yocto BSPs 

ssi2 dts :  linux/arch/arm/boot/dts/imx6qdl-sabresd.dtsi

linux-imx.git - i.MX Linux Kernel 

Best regards
igor
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GregT
Contributor III

Thanks Igor.  Using the Patchwork link I added an audmux node, but it didn't help with the sound.

&audmux {
   status = "okay";
   pinctrl-0 = <&pinctrl_audmux>;

   ssi2 {
      fsl,audmux-port = <2>;
      fsl,port-config = <0x00000800 0x0000a000>;
   };

   pins5 {
      fsl,audmux-port = <6>;
      fsl,port-config = <0x8c400800 0x00002000>;
   };

};

I do see an error when running the alsa speaker-test.  Not sure what the error means.

$ speaker-test

Write error: -5,Input/output error 

xrun_recovery failed: -5,Input/output error 

Transfer failed: Operation not permitted 

 

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GregT
Contributor III

I was finally able to get a scope on the MCLK pin of the TLV320AIC3256 and it has no clock on it in the linux 4.9 version.  The linux 3.0 version has a nice 4096000 hz clock on it.  I would have thought the CLKO1 should be there based on the device tree entry

MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x130b0

Maybe there is a problem in the assigned-clocks.  I'm not sure how to interpret the device tree entries below.  Any help would be appreciated.

&clks {
        assigned-clocks = <&clks IMX6QDL_CLK_PLL4>,//0
                          <&clks IMX6QDL_PLL4_BYPASS>,//1
                          <&clks IMX6QDL_CLK_SSI1_SEL>,//2
                                                  <&clks IMX6QDL_CLK_SSI1>,//3
                          <&clks IMX6QDL_CLK_SSI2_SEL>,//2
                                                  <&clks IMX6QDL_CLK_SSI2>,//3
                                                  <&clks IMX6QDL_CLK_CKO2_SEL>,//4
                                                  <&clks IMX6QDL_CLK_CKO2>,//5
                                                  <&clks IMX6QDL_CLK_CKO1_SEL>,//6
                                                  <&clks IMX6QDL_CLK_CKO1>;//7
        assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>,//0
                                 <&clks IMX6QDL_CLK_PLL4>,//1
                                 <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>,//2
                                                                 <0>,//3
                                 <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>,//2
                                                                 <0>,//3
                                                                 <&clks IMX6QDL_CLK_SSI2>,//4
                                                                 <0>,//5
                                                                 <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;//6
        assigned-clock-rates = <688128000>, <0>, <0>, <4096000>, <0>, <4096000>,<0>,<4096000>,<0>,<4096000>;
};
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GregT
Contributor III

From looking at the CCM registers it does not look like the pll4 is getting turned on when using linux 4.9 as shown in bit 31 being 0 below.

mem 0x20c8070 w

Value at 0x20c8070: 0x0000101C

For linux 3.0 it is locked which is indicated by bit 31 being high.

mem 0x20c8070 w

Value at 0x20c8070: 0x8010201C

Any ideas on how to modify the device tree to make sure pll4 is turned on?

Thanks,

Greg

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GregT
Contributor III

I was able to get the clocks turned on by modifying clk-imx6q.c and setting up the device tree.  Below are the code changes and the device tree.  I would have thought defining the clocks in the device tree would enable the clocks but it does not.

/*
* Let's initially set up CLKO with OSC24M, since this configuration
* is widely used by imx6q board designs to clock audio codec.
* Except if this is Scrooge with the TLV320AIC3256
*/
if (!IS_ENABLED(CONFIG_SND_SOC_IMX_TLV320AIC3256)) {
   printk(KERN_INFO "Scrooge TLV320AIC3256 not enabled\n");
   imx_clk_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], clk[IMX6QDL_CLK_OSC]);
}
imx_clk_set_parent(clk[IMX6QDL_CLK_CKO], clk[IMX6QDL_CLK_CKO2]);

/* turn on PLL4 if we are using the TLV320AIC3256 driver */
if (IS_ENABLED(CONFIG_SND_SOC_IMX_TLV320AIC3256)) {
   imx_clk_prepare_enable(clk[IMX6QDL_CLK_PLL4]);
   imx_clk_prepare_enable(clk[IMX6QDL_PLL4_BYPASS]);
   imx_clk_prepare_enable(clk[IMX6QDL_CLK_PLL4_AUDIO]);
   imx_clk_prepare_enable(clk[IMX6QDL_CLK_SSI2_SEL]);
   imx_clk_prepare_enable(clk[IMX6QDL_CLK_SSI2]);
   imx_clk_prepare_enable(clk[IMX6QDL_CLK_CKO2_SEL]);
   imx_clk_prepare_enable(clk[IMX6QDL_CLK_CKO2]);
   imx_clk_prepare_enable(clk[IMX6QDL_CLK_CKO]);
   printk(KERN_INFO "Turned on PLL4, PLL4_BYPASS, PLL4_AUDIO, SSI2_SEL, SII2, CKO2_SEL, CKO2, CKO\n");
}

&clks {
assigned-clocks = <&clks IMX6QDL_CLK_PLL4>, //0
                              <&clks IMX6QDL_PLL4_BYPASS>, //1
                              <&clks IMX6QDL_CLK_PLL4_AUDIO>,//2
                              <&clks IMX6QDL_CLK_SSI2_SEL>, //3
                              <&clks IMX6QDL_CLK_SSI2>, //4
                              <&clks IMX6QDL_CLK_SSI1_SEL>, //5
                              <&clks IMX6QDL_CLK_SSI1>, //6
                              <&clks IMX6QDL_CLK_CKO2_SEL>, //7
                              <&clks IMX6QDL_CLK_CKO2>, //8
                              <&clks IMX6QDL_CLK_CKO>; //9
assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>, //0
                                          <&clks IMX6QDL_CLK_PLL4>, //1
                                          <&clks IMX6QDL_PLL4_BYPASS>,//2
                                          <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>, //3
                                          <0>, //4
                                          <&clks IMX6QDL_CLK_PLL4>, //5
                                          <0>, //6
                                          <&clks IMX6QDL_CLK_SSI2>, //7
                                          <0>, //8
                                          <&clks IMX6QDL_CLK_CKO2>; //9
assigned-clock-rates = <688128000>, // 0
                                       <0>, // 1
                                       <0>, // 2
                                       <0>, // 3
                                       <4096000>, // 4
                                       <0>, // 5
                                       <4096000>, // 6
                                       <0>, // 7
                                       <4096000>; // 8
                                                            // 9 Unchanged from CKO2
};

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GregT
Contributor III

BTW, there was another issue blocking the clocking.  In the audmux section I was missing pinctrl-names = "default";  That line must set the pad mux registers for the pin_ctrl audmuxgrp earlier in the device tree file given in an earlier post.

&audmux {
   pinctrl-names = "default";
   status = "okay";
   pinctrl-0 = <&pinctrl_audmux>;

   ssi2 {
      fsl,audmux-port = <2>;
      fsl,port-config = <0x00000800 0x0000a000>;
   };

   pins5 {
      fsl,audmux-port = <6>;
      fsl,port-config = <0x8c400800 0x00002000>;
   };

};

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marcosal
Contributor II

Hi Greg,

At the end were you able to port your audio driver? I am facing a similar situation porting an audio driver over ssi2 with a dummy codec since the custom board doesn't have a real hardware audio codec.

I was able to register the sound and I see in the boot logs that the alsa driver is shown.

Right now my problem is an write/read error when I try to send a file using cat to the /dev/audio

cat file.wav > /dev/audio

and I get an write/read error. Once you had your clocks configured everything worked fine?

Thanks!

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