I have some doubts regarding the HDMI clock sources and enabling spreadspectrum for HDMI. I am working on a custom board which has IMX6Quad. I have listed my questions below.
1) Can we enable spreadspectrum for HDMI interface? If yes, How should we enable spreadspectrum for HDMI. Is it the similar process as done for LVDS/LCD interface, where the parent clock is changed to PLL2_PFD2 for the IPU1_DI0 interface and enabling SS in PLL2?
2) I understand that there is VIDEO_27M clock source which is used to generate the TMDS signal from HDMI_PHY and it seems the IPU output is given to HDMI TX controller. How are these two clocks interlinked? will enabling SS in IPU output gets reflected on TMDS signals?
Thanks,
Sudar.K.B.
Hi Sudar
you are right that spread spectrum should be provided by phy,
but I am afraid that i.MX6Q hdmi phy is not able to produce spread spectrum
clock, opposite to sata or pcie, where such descriptions can be found in reference manual.
For emi issues one can slightly tweak HDMI preemph and termination values,
described in sect.2 "Software configuration and procedures"
AN4671 (rev.0, 4/2013) "i.MX 6 Series HDMI Test Method for
Eye Pattern and Electrical Characteristics" and
Table 34-13 "Driver Voltage Level", Table 34-6 "Single-Ended Source
Termination Resistance Settings" i.MX6DQ Reference Manual
Best regards
igor
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But what about this documents - https://community.nxp.com/docs/DOC-100036 ?
this document is about pll2 spread spectrum, not hdmi phy pll.