Hi,
Does NXP have any recommendations for adding source series resistance to the LVDS output of the SoloX? We would like to slow down the edge rates. We are running the LVDS at 24.58 MHz.
We are trying to lower the amount of 688 MHz (LVDS parent clock) noise we are seeing in emissions scans. We were able to add 10 pF 0201 capacitors at each LVDS pair between the vias under the SoloX and see the emissions level go down. But we aren't able to test adding source series resistors because the traces are on internal layers until they reach the connector.
We use a deserializer (DS90CF384) to drive a RGB parallel LCD on another board with 100 ohm termination resistors for each LVDS pair.
This is our LVDS clock tree:
pll5 0 0 688239984 0
pll5_bypass 0 0 688239984 0
pll5_video 0 0 688239984 0
pll5_post_div 0 0 172059996 0
pll5_video_div 0 0 172059996 0
ldb_di0_sel 0 0 172059996 0
ldb_di0_div_7 0 0 24579999 0
