SoloX RMII ENET1_REF_CLK Jitter

キャンセル
次の結果を表示 
表示  限定  | 次の代わりに検索 
もしかして: 

SoloX RMII ENET1_REF_CLK Jitter

1,792件の閲覧回数
scottgauche
Contributor I


Hi,


Is there a way to determine the jitter specifications of the ENET1_REF_CLK for a RMII interface?

Thanks,

Scott

ラベル(2)
0 件の賞賛
返信
3 返答(返信)

1,222件の閲覧回数
art
NXP Employee
NXP Employee

For the RMII interface, the reference clock should be 50MHz +/- 50ppm.


Have a great day,
Artur

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

0 件の賞賛
返信

1,222件の閲覧回数
scottgauche
Contributor I

We are using a 24 MHz +/- 30 ppm crystal for the SoloX XTAL.  Similar to what is used on the SoloX Sabre board.  But that is the frequency tolerance, we are looking for a way to figure out if there is a jitter specification for what the SoloX is able to output for the 50 MHz RMII clock to the PHY.

0 件の賞賛
返信

1,222件の閲覧回数
art
NXP Employee
NXP Employee

No, there is no strict jitter specification for this clock. The meaning is that any frequency fluctuation of the clock must remain within this 50MHz +/- 50ppm range.

Artur

0 件の賞賛
返信