Set DDR bus size to 32 bits

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Set DDR bus size to 32 bits

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AlbertT
Contributor V

Hello !

I have an iMX6 Dual Sabre SD (SABRE Platform for Smart Devices Based on the i.MX 6 Series Product Summary Page) with 1Gb of DDR3 (2*512 I guess since I see two chips on the board but I'm not sure of that) and I would like to limit the DDR bus to 32 bits instead of 64 bits.

I found this : Re: iMX6 DualLite with Micron DDR3 (2 x MT41J128M16HA) so I tried to add this lines in my flash_header.S :

MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x000, 0x83190000)          //limit to 32 bits

MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x818, 0x00000000)    /* Disable ODT. TEST*/

MXC_DCD_ITEM(85, MMDC_P1_BASE_ADDR + 0x818, 0x00000000)

But I get the same time for reading my uImage in u-boot (I've added some timers there) so I guess my modifications changed nothing. So did I follow the good way to limit the DDR bus ? And how can I check if my modifications are OK ?

Thanks !

EDIT : or should I just replace the

#define CONFIG_DDR_64BIT /* for DDR 64bit */

by

#define CONFIG_DDR_32BIT


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AlbertT
Contributor V

I've tried this: https://community.nxp.com/docs/DOC-93963

But this doesn't work either

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admin
Specialist II

From xiaoli.zhang:

Please refer toHow to Create i.MX6 32bit DDR3 Script Based on 64bit DDR3 Script.

If you changed DDR from 64bit to 32bit on MX6SabreSD Board, please note that you must reduce DDR size:

/*-----------------------------------------------------------------------

* Physical Memory Map

*/

#define CONFIG_NR_DRAM_BANKS    1

#define PHYS_SDRAM_1            CSD0_DDR_BASE_ADDR

#define PHYS_SDRAM_1_SIZE       (512 * 1024 * 1024)

#define iomem_valid_addr(addr, size) \

        (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))


Regarding DDR performance gap, you can run some tests which require high-bandwidth. Then you can see performance gap due to bus width.


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AlbertT
Contributor V

Ok I did some tests and here are my results : I can define CONFIG_DDR_32BIT but that's works only if I change the DDR size to 512Mo. And I don't understand why ...

Why is the DDR bus size linked to the DDR size ?

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AlbertT
Contributor V

Hello,

Thanks for your feedback. I did not change this define so I think that's why that didn't worked. Instead I used the patch that emulate a solo on a dual or quad and that seems to work well.

But I will definitely try your solution !

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