@AldoG This not resolved our issue. Still we are facing the same delay on CANFD transfer.
Please see below.
It will transfer a bunch data at 597 th ms then there is a delay of 42 milli second and then again it will transfer a bunch of data at 640 th ms. This continues. Observed a delay 42 or 43 milli seconds.
Still I am observing the same delay between the transfer of CANFD data.
@AldoG Earlier I mentioned that we are observing a delay of 42/43 ms . We reached in this calculation by checking the CPU terminal timestamp. It was wrong. We have added timestamp reading inside spi driver then we observed that there are no abnormal delay of 42/43 ms. But still we are observing a delay of ~0.9 ms between each transfer.
We probed the CS, CLK, MOSI and interrupt pin. On probing we observed that interrupt is happening on every 0.8 ms and the gap between 2 continuous CS low & high is 0.9 ms (Not between single CS low & high, you can see a stream of CS line going low and high then there is a long gap). We are able to receive data in the reception side also on every 0.9 ms. Multiple no of clocks also triggering at the same time. Please see below trace.
Even after triggering multiple clock, CS pin, I was able to receive 1 data at reception side and interrupt is holding high for a long time. Is that expected interrupt holding high for a long duration?
We observed that 4 byte data is transferring while CS going low and high. Is it possible to transfer more than 4 bytes on a single CS going low & high.
One more interesting thing we observed is without transferring any data, We are getting pulses from the probed lines CS, interrupt, clock. Below is the trace for that.
Regards
Roshan Mohammed PP
