SPDIF Rx Clock (SPDIF_SR_CLK) Jitter

[yoshida_satoru]

I'm planning to use the SPDIF from the i.MX RT 1060.
The manual says that the SPDIF receiver can output the SPDIF Rx Clock (SPDIF_SR_CLK).
What is the jitter of the SPDIF Rx Clock (SPDIF_SR_CLK)?
Is there any information about jitter in the manual?

[Gavin_Jia]

Hi @yoshida_satoru ,

Thanks for your interest in NXP MIMXRT series!

There is no manual pointing to this data. For a specific module, the jitter of the clock needs to be satisfied by an external device. For MCUs, it is only the choice of crystal that needs to satisfy the hardware design guide.

The crystal used on the RT1060 EVK is this part. 7V240000002 with an ESR of 60 ohms, a 30 ppm crystal. Fairly typical crystal. 

Best regards,
Gavin

[yoshida_satoru]

Thanks Gavin.

I have a question about the 7V240000002 crystal.
Is 7V240000002 correct as the one in the red box in the screenshot below?
(The screenshot below is an excerpt from the RT1060 EVK circuit diagram)

[Gavin_Jia]

Hi @yoshida_satoru ,

Yes, it is. 

[yoshida_satoru]

Thanks Gavin.

The reference manual (IMXRT1060RM.pdf) has the following explanation in 40.3.1.8:

> The circuit will measure the frequency of the incoming clock as a function of the BUS_CLK.

What does BUS_CLK refer to here?
Is it something generated from 7V240000002?

If it is something generated from 7V240000002, does that mean that the precision of 7V240000002 affects the jitter of the SPDIF Rx Clock (SPDIF_SR_CLK)?

[Gavin_Jia · Accepted solution]

Hi @yoshida_satoru ,

The BUS_Clock is IPG_CLK. SPDIF_RX uses the system's IPG_CLK (150MHz) as a reference when detecting the signal. In this case, if there is any frequency fluctuation or instability in IPG_CLK, jitter may be introduced in the measurement of SPDIF_SR_CLK. 

While this is true in principle, I think the biggest source of jitter is still the SPDIF input signal.

Bests,
Gavin