Hi Evan
seems this behaviour complies with description in Table 6-8.
Power mode transitions i.MX7D Reference Manual
"ON, first time - Either coin cell or SoC power supply is connected to SNVS."
http://cache.nxp.com/files/32bit/doc/ref_manual/IMX7DRM.pdf
I am not aware of special SNVS register settings for case when power is
removed from the board, but when power is removed abruptly there may be
corruption of nand or emmc images, if there is current data transfer from them.
Best regards
igor
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