SGTL5000 and Non-Standard Sample Rates

[matthiash]

Dear all,

I'm in the process of developing a minimalist USB audio interface around the SGTL5000 and competition's LPC1347 (clocked at 72 MHz), and I am having a hard time figuring out the best clock configuration. Since MCLK is going to be obtained by integer frequency division, it is likely going to have to be 12 MHz. From what I can tell, this leaves me with three options:

1. Using the PLL and having the SGTL as I2S master (inconvenient for several reasons),
2. an "odd" sample rate of 46.875 kHz (12000000 Hz / 256, which would be by far my preferred choice), or
3. a just as hacky solution with 44.1 kHz LRCLK, 1.5 MHz SCLK, and transmission breaks in between samples.

In order to figure this out, I would appreciate knowing more about how the SGTL internally synchronizes to I2S data - can I, for instance, use a higher SCLK and just wait with the transmission of the next sample until the end of the LRCLK interval? Are there any known cases where such situation has been successfully resolved with the SGTL as I2S slave? What would be the corresponding settings?

Thanks,

Matthias

[igorpadykov]

Hi Matthias

one can use SGTL5000 internal PLL for obtaining necessary frequencies.

This is described in SGTL5000 p.14

sect.2.2.2 PLL Configuration AN3663 AN3663, SGTL5000 Initialization and Programming

Regarding usage "higher SCLK", I am afraid SGTL5000 does not support such kind of algorithm.

Best regards

igor

[matthiash]

And ... we have audio out! (It also helps to probe the line outs, not the line ins :smileyhappy:)

Thanks Igor for your smooth response.

Matthias

[matthiash]

Thank you for your reply. From the manual, I take it that using the PLL requires that the SGTL become master on the I2S bus, correct?

[igorpadykov]

yes correct, as described in SGTL5000 p.18 :

The I2S_LRCLK and I2S_SCLK can be programmed as

master (driven to an external target) or slave (driven from an

external source). When the clocks are in slave mode, they

must be synchronous to SYS_MCLK. For this reason the

SGTL5000 can only operate in synchronous mode (see

Clocking) while in I2S slave mode.

In master mode, the clocks are synchronous to

SYS_MCLK or the output of the PLL when the part is running

in asynchronous mode.

~igor

[matthiash]

Thank you. Just implemented that, and by accident also found out that the sample rate can in fact be set to "odd" values, at least as long as they're in the interval of 44.1 to 48 kHz. To achieve f_target (in kHz), the PLL output freq (also in kHz can be calculated as pll_output_freq = 196608 / 48 * f_target. For f_target = 44.1 kHz, this results in pll_output_freq=180633.6 kHz. So the divider for 48 kHz is 16.384 -- accidentally rounding it to 16.000 results exactly in a sample rate of 46.875 kHz :-)