Dear Support,
I am working on a imx8mm SoC in a bare-metal environment. My goal is to use SDMA2 with SAI2 RX. Firstly, I have started with SDMA1 and UART1 TX. Once I succeeded, I have migrated to SDMA2 (SDMA2/3 is dedicated for SAI) and failed early in SDMA2 setup process.
I have prepared the following scenario to recreate the issue:
1. Prepare channel contexts, channel control blocks, buffer descriptors in ARM RAM.
2. Enable SDMAx clock:
- SDMA1: run AHB from PLL1/6 resulting in 133 MHz, ungate CCGR=58
- SDMA2: run AUDIO_AHB from PLL1/2. resulting in 400 MHz, ungate CCGR=59
3. Setup SDMA registers (MC0PTR, DSPOVR, EVTOVR, HOSTOVR, CONFIG, CHNENBL, CHENPRI, CHN0ADDR, INTRMASK)
4. Setup a buffer_descriptor_0 for Channel0 to load ChannelN context into SDMA RAM (using SETCTX bootscript command)
5. Write to HSTART SDMA register to trigger Channel0 context loading
6. Busy-wait for STOP_STAT register to have bit0 cleared
7. Observe buffer_descriptor_0 DONE bit - it shall be cleared (signalling that SDMA finalized processing the buffer)
8. Proceed with peripheral interaction etc.
The step (7) fails on SDMA2 - DONE bit is never cleared, so any subsequent operation on SDMA2 does not make sense (as context is not set - I have tried other commands like GETDM as well with same result). Setting INTERRUPT bit also does not cause the interrupt to occur, further confirming there is something wrong with SDMA2 buffer descriptor processing. I observe STOP_STAT to go from 0x1 to 0x0, which implies that channel0 starts, but for some reason skips buffer_descriptor_0, apparently.
Conclusion is that the basic SDMA usage scenario described above works for SDMA1, but does not work for SDMA2 (also does not work for SDMA3).
Question: is there any SDMA2/SDMA3-specific configuration that lack of would result in such regression when compared to SDMA1 ?
Best regards
