SDMA for PCIe

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SDMA for PCIe

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mitchellcox
Contributor I

Hi All

I've been looking at using the i.MX6Q's PCIe for both endpoint and root complex and since there is no DMA engine on the PCIe built it's a bit difficult to write linux drivers for high data throughput. I have two things I'd like to clarify:

1) Would it be possible to use the SDMA to copy data out of the PCIe space (0x01000000 say) into a location in memory to 'emulate' the PCIe having a true DMA controller?

2) I have been studying the PCIe specs from PCI-SIG as well as the reference manuals, etc. I am unsure about exactly how the memory BARs work on the EP: is it possible to simply use the iATU for 'DMA'? For example, I think that I could map BAR0 to a region that I kzalloc on the EP in the driver that has some arbitrary data structure in it. When the RC writes data in the format of this data structure to the EP's BAR0, would it end up in my kzallocd area? Does this same logic apply from the EP back to the RC, except that the address would have to be hardcoded since the concept of BARs doesnt apply to RC's?

In this case, only the sender of the data needs to use the SDMA to move data from where it is to where it needs to be for PCIe, bringing me to 1), above. Perhaps I've missed the boat somewhere!

Sorry if this is pushing this question too far, but I'm sure others are wondering the same things!

Hopefully I've been clear enough! There's a major learning curve involved with PCIe and the iMX way...

Thanks!

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CarlosCasillas
NXP Employee
NXP Employee

Hi Mitchell,

Regarding your question #1, I'm afraid that it is not possible. Bus doesn't allow SDMA access PCIe SPACE.

PCIe space can be access only two bus master, one is ARM, the other is IPU.

ARM can write data to the remote DDR by PCIe.  RC can write data to EP memory. EP can write data to RC memory.


Hope this will be useful for you.
Best regards!
/Carlos

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CarlosCasillas
NXP Employee
NXP Employee

Hi Mitchell,

Regarding your question #1, I'm afraid that it is not possible. Bus doesn't allow SDMA access PCIe SPACE.

PCIe space can be access only two bus master, one is ARM, the other is IPU.

ARM can write data to the remote DDR by PCIe.  RC can write data to EP memory. EP can write data to RC memory.


Hope this will be useful for you.
Best regards!
/Carlos

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Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

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mitchellcox
Contributor I

Hi Carlos

Thanks for the reply! Just to clarify:

"ARM can write data to the remote DDR by PCIe.  RC can write data to EP memory. EP can write data to RC memory"

So the RC can write to any area in EP memory (iATU inbound on EP) and EP can write anywhere in RC (iATU inbound on RC)?

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CarlosCasillas
NXP Employee
NXP Employee

Hi Mitchel,

Additional information:

Normally and End Point (EP) will use BAR match mode and a root Complex (RC) will use Address match mode as an RC normally has no BAR’s implemented.


Hope this will be useful for you.
Best regards!
/Carlos

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Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

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CarlosCasillas
NXP Employee
NXP Employee

Hi Mitchell,

We are reviewing your request internally, you will get a response soon. 

Best regards!

/Carlos

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