SABRE-SDB for i.MX 6 Series - PCB Stack-up / Routing Problem

[Jim_Herrmann]

Hello - I am about to dive into implementing a custom embedded design with the i.MX6Q. To help accelerate the design process, I am reviewing the schematic, BOM, and PCB layout files that are provided with the SABRE-SDB. After just a very brief review of the 8-layer PCB stack-up and routing, it is readily apparent that this PCB layout is problematic and falls well short of my expectations for design work from Freescale. The PCB layout provided does not meet the routing guidelines specified in the Freescale  IMX6DQ6SDLHDG Hardware Development Guide (Section 2.5.8): "High speed signals (DDR,..) must not cross gaps in the reference plane. Avoid creating slots, voids, and splits in reference planes. Review via voids to ensure they do not create splits (space out vias)".

The 8-layer stack-up deployed has numerous cuts / moats in the (2) DC power planes (layers 4 & 5). These cuts are to be expected - but must be avoided by trace routing. Based on the dielectric thicknesses called out in the .DSN file, the asymmetric stripline routing (layers 3 & 6) will image ~40% of their return current onto these cut-up power planes (and ~60% onto the continuous GND planes (layers 2 and 7). Please comment on how it is OK for this layout to ignore both industry best practice and the IMX6DQ6SDLHDG HW Dev Guide which specify that high speed traces must reference only continuous planes.

Given the extent to which design teams take reference platform schematics and PCB layouts as verbatim, then I think it is critical to openly discuss potential design performance shortcomings. Has any EMI emissions testing been performed on this PCBA? If yes, can the results be posted?

Thanks,

Jim

[TheAdmiral]

Hi Jim,

To say that the SABRE-SDB board is a reference design is really not a good characterization of the board or its purpose. The SABRE-SDB is a software development platform.

What is the difference? Well, a software development platform has many additional features that may, or may not, be used as would be necessary to begin general work on software while a more custom board is in initial development. In addition, a software development platform would go out of its way to split voltage supply rails in order to allow current measurements for determening power measurements while the board was in use during various operating states of the software.

Simply put, the board is not optimized for sale in the consumer space. There are too many requirements on the board that are simply there for experimentation and development.

And what changes would I make for a board intented in the consumer space? First, I would remove all the different NVCC_ rails and connect all the NVCC_ supply pins directly to the main 3V3 rail. If I needed a NVCC_1V8 rail at all, I would judiciuosly place it in a location where it would not split the other major rails. I would also combine VDDARM_IN and VDDSOC_IN into one power rail. Depending on whether I wanted to keep RTC and security functions going when the rest of the processor is completely shutdown, I would also consider combining VDDHIGH_IN with VDD_SNVS_IN. That will essential cut the number of solid voltage planes that need to be routed underneath the processor down to three and one-half: VDDARM/SOC, VDD_DDR (which only needs to be routed under one side of the processor), 3V3, and the half-plane would be VDDHIGH_IN/VDD_SNVS_IN depending how you would like to handle that. Is Freescale going to produce a board like that? No. Freescale management is limiting resources to a minimum board set to accomplish software development testing.

That would essentially answer all the issues you were concerned about. I am in no way conerned about the DDR3 layout. It performs very well at much higher than rated frequencies over temperature ranges of -40C to +85C

So if the sheer number of voltage rails underneath the processor is an issue, why don't we go to more layers? Well, we have many customers that want to build a board as cheaply as possible. In fact, we have customers who ask why we can't route this out on a four layer board. So, another mandate placed on the board is that we route it on an 8-layer board. This we have done, and this we have demonstrated works.

>> Please comment on how it is OK for this layout to ignore both industry best practice and the tIMXDQ6SDLHDG HW Dev guide which specity tht high speed traces must reference only continuous planes.

Well, actually, we did not ignore the points you bring up. Instead, we were forced to compromise in some areas in order to produce a board that meets the requirements set before it. So is this OK? The board is working as designed in every way: It met all of it's design goals.

To answer your question about EMI: Yes, the SABRE-SDB board has been through official FCC/CE testing (at a certified test house) for EMI. Please note, the EMI testing is highly dependent on software settings, which for a board designed as a software development platform, is changing daily. Also note that EMI testing is done on the expected consumer use case, and Freescale did not perform testing on more than one board configuration case. (If you are concerned about EMI and are planning to use the HDMI output, I would plan on using CMCs on the HDMI data lanes. That would be one change I would make.) Emmissions for DDR3 operations was not seeen as a problem, and can actually be made even better by reducing the BSP drive strength settings (DSE) several settings.

In summary, the board is not a reference design. We do not expect our customers take take the design and build it as is. It does, however, work and can be used by customers as is (as proven by many units working consistently well since the introduction of the SABRE-SDB). So if customers do copy our layout explicitly, they will have a successful board. Customers who know better are encouraged to make modifications to suit their specific needs.

Cheers,

Mark

[Jim_Herrmann]

Hello Mark,

Thank you for your reply. Your justification for having, in your words, a HW design that is not optimized for the consumer space, seems to be a rather poor argument for releasing a board design that violates your own published PCB layout guidelines for the i.MX 6. You may consider it a SW dev platform, but a segment of your customers obviously consider it to be a HW reference as well - it has the *Freescale* name on it - just read the posts on this forum. Given your characterization of the SABRE-SDB as not being optimized, but as a general purpose platform, then why would you allow an arbitrary layer count goal from Marketing cause you to violate your design rules? Going to 10 layers would have eliminated the layout guidelines violations, and your customers would not have to try to interpret why Freescale did not follow its own layout recommendations.

With respect to EMI, your response "has been through official FCC/CE testing" is too vague to draw any real conclusions. Did the board actually pass - if yes, then did it pass Class A or Class B levels? Suggesting that you'd like to add CMC's to the HDMI interface indicates that the 8-layer PCB layout has common mode noise issues...a predictable outcome. What IO cables were installed during the EMI testing? Were any cable ferrites installed? My 10-layer i.MX 6 just passed FCC Class B with several dB of margin w/ several IO cables and no cable ferrites whatsoever. for future platform designs - I urge you to push back hard on arbitrary layer count goals - follow your specified guidelines - your end customers will be less confused and they will gain insight from inspecting how the physical layout you implemented met those guidelines.

Thanks,

Jim