Hi Igor,
I would like to reset the first A53 core and halt it at the reset vector.
For this I am using the RMR_EL2.RR bit.and for catching at the reset, I am setting EDECR.RCE bit.
The core is getting reset and it starts running. So when i check thestatus of EDECR, it has been cleared.
What kind of reset it do when RR is set? A warm reset or cold reset? If it is a warm reset the register should not clear isnt it?
Is ARMv8-A DoPD is implemented in iMX8QM? If it is not, EDECR comes in Debug power domain as per ARM v8-A specification.
So it should not clear even if a cold reset is done. What could be the reason for the register is getting reset?
Regards,
Ranjith