Regarding CSI Port 2 Data Rate on i.MX8MP

[kayakaantuna]

Hello everyone,

I have a question regarding the i.MX8MPQ SoC's CSI Port2.

According to the documented CSI limitations for both ports, I am able to capture frames without any issues on CSI Port 1 at a 1.5 Gbps data rate. However, on CSI Port 2, I can only obtain a partial image at 400 Mbps. Our goal is to stream 1920×1280 UYVY on CSI Port 1 and 1600×1300 RAW8 on CSI Port 2. At the moment, CSI Port 2 only produces a 1600×867 image and increasing the data rate beyond 400 Mbps results in no frame output at all.

Based on my calculations, CSI Port 2 should be capable of approximately 1 Gbps per lane:

lane_rate ≈ PixelClock * BPP / lanes

lane_rate ≈ 266000000 * 8 / 2 =~ 1 Gbps per lane (this should be the limit for 8 BPP)

lane_rate ≈ 200000000 * 8 / 2 = 800 Mbps per lane  (< 1.5 Gbps limit)

Given this, CSI Port 2 should theoretically support the required data rate, yet it cannot operate above ~400 Mbps. This issue does not appear on CSI Port 1, where everything functions as expected.

Can someone help me with this issue ? Any directions is appreciate it.

[Chavira]

Hi @kayakaantuna,

The i.MX8MP SoC integrates two MIPI CSI interfaces, each connected through a dedicated D-PHY block. According to the reference manual, both CSI ports can theoretically support up to 1.5 Gbps per lane when configured correctly. Each port can operate with up to four lanes, and the actual throughput depends on lane count, pixel format, and clock configuration. Your calculation of approximately 1 Gbps per lane for RAW8 at 1600×1300 resolution is correct and falls within the hardware limits.

However, the observed limitation on CSI Port 2—where it fails above ~400 Mbps—suggests a configuration or resource bottleneck rather than a fundamental hardware restriction. One common cause is incorrect lane configuration. If CSI2 is operating in two-lane mode instead of four, the maximum achievable bandwidth will be halved. Another factor is the clock tree: each CSI port has its own clock root managed by the Clock Control Module (CCM). If the CSI2 root clock or PLL settings are capped at a lower frequency, the D-PHY cannot reach the expected data rate.

Beyond PHY and clock settings, the Image Sensor Interface (ISI) plays a critical role. When two cameras are active, the ISI shares resources and may throttle one port to prevent DMA overruns. The manual indicates that simultaneous dual-camera operation supports up to 1080p at 80 fps per stream, which implies bandwidth sharing.

Software configuration is another key area. In Linux BSPs, the device tree defines CSI parameters such as lane count and PHY speed. If CSI2 is incorrectly set to a lower phy-speed or fewer lanes, the driver will enforce these limits. Testing CSI2 in single-camera mode at higher speeds can help determine whether the issue is resource contention or configuration.

[kayakaantuna]

Hi @Chavira ,

Thank you for your suggestions however, when I try to operate on 4 lane mode it seems I can't get a frame at all even in 400Mbps ? Does the pixel clock is limiting us ?

Here is my settings:

```

&mipi_csi_0 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
no-reset-control;
 
port@0 {
reg = <0>;
mipi_csi0_ep: endpoint {
remote-endpoint = <&camera1>;
data-lanes = <2>;
csis-hs-settle = <17>; // 1.5Gbps 
csis-clk-settle = <0>;
csis-wclk;
virtual-channel = <0>; 
};
};
};

&mipi_csi_1 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
no-reset-control;

port@1 {
reg = <1>;
mipi_csi1_ep: endpoint {
remote-endpoint = <&camera2>;
data-lanes = <2>;
csis-hs-settle = <17>; // 800Mbps 
csis-clk-settle = <0>;
csis-wclk;
virtual-channel = <0>; 
};
};
};

```

[Chavira]

Hi @kayakaantuna,

Could you please share the complete device tree file?

Which camera model are you using?
Which BSP (Board Support Package) version are you working with?

What board are you using?

I’m asking these questions to better understand the context of your current configuration and provide accurate guidance.

Best regards,
Chavira

[kayakaantuna]

Hi @Chavira ,

> Could you please share the complete device tree file?

- Please find it in attachments.

> Which camera model are you using?

- ISX021 and OV2311 with max96716/96717 GMSL.

> Which BSP (Board Support Package) version are you working with?

- lf5.10.y the kernel version I'm using currently.

> What board are you using?

MYD-JX8MPQ Development Board

Oh by the way, I'm able to stream 4 lane 1.5Gbps on CSI Port 1. But nothing on CSI Port 2 side.

Thanks.

[Chavira]

Hi @kayakaantuna,

I can´t find the drivers that you are trying to use.

Are you using a custom drivers or drivers provided by myir tech?

[kayakaantuna]

Hi @Chavira,

I can’t share the drivers since they are proprietary to a company, unfortunately. However, I can confirm that both of them work on CSI Port 1. I’m able to get a stream without any limitations on the CSI data rate or anything else on CSI Port 1.

Thanks

[Chavira]

Hi @kayakaantunam,

You can refer to the existing camera configurations and device tree files available for the i.MX8MP-EVK board or similar boards from our partners on GitHub. These resources should help you set up your configuration.

Please check the following link for reference:
imx8mp-evk.dts 

Best regards,
Chavira

[kayakaantuna]

Hi @Chavira,

I’ve already done that, and I can successfully get a stream from both of our cameras on CSI Port 1. The issue is with configuring CSI Port 2. Could you please help me with that?

To clarify, I’m able to get a 4-lane stream on CSI Port 1 at 1.5 Gbps per lane. However, when I switch to CSI Port 2—even after lowering the data rate to, say, 800 Mbps per lane—I’m not able to get any frames at all. I’d appreciate your guidance on what configuration settings I should try for CSI Port 2.

Thanks!

[Chavira]

Hi @kayakaantuna,

Unfortunately, I’m unable to recommend a specific configuration because I don’t have access to your source code or device tree files for analysis.

If you can share those details or provide more context about your setup, I’d be happy to assist further.

[kayakaantuna]

Hi @Chavira ,

I already share you my device-tree file, you can see it as I send it as "myd-jx8mp-base.dts" few comments above. I will attach it once again. The driver source codes I can't share unfortunately.

Do have a look please.

As for my setup I think below image would help.

Thanks.