Recommended layout for 64-bit ECC DDR3L with i.mx6Q?

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Recommended layout for 64-bit ECC DDR3L with i.mx6Q?

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akohlsmith
Contributor II

I've been going over the hardware development guide and the section on DDR3 routing is especially informative. It appears that routing by byte lane and using fly-by routing with write levelling is probably the best approach for layout, but the documentation stops short of giving recommendations for a 4GB, 5-chip DDR3L layout (4 devices + 1 for ECC).

Has anyone done this kind of layout with an i.MX6? Do you have recommendations on the layout? Are there any known gotchas or things to avoid when doing an ECC layout with the i.MX6?

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Yuri
NXP TechSupport
NXP TechSupport

The i.MX6 itself does not support DRAM ECC, therefore ECC approach may be implemented
only via external memory controller, supporting ECC. Freescale does not have
such design and recommendations about it, sorry. Perhaps it would be better to apply to
devices of
QorIQ LS architecture, which support (external) memory ECC, and will be launched
soon.

  Layerscape Architecture|Freescale

Have a great day,
Yuri

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Yuri
NXP TechSupport
NXP TechSupport

The i.MX6 itself does not support DRAM ECC, therefore ECC approach may be implemented
only via external memory controller, supporting ECC. Freescale does not have
such design and recommendations about it, sorry. Perhaps it would be better to apply to
devices of
QorIQ LS architecture, which support (external) memory ECC, and will be launched
soon.

  Layerscape Architecture|Freescale

Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

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akohlsmith
Contributor II

Thank you for pointing out to me that the i.MX6 does not support ECC. I could have sworn that I saw a 9th byte lane on the DDR interface but clearly that is not the case.

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