Read and write cycle delayed at the output of FTDI FT2232H

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Read and write cycle delayed at the output of FTDI FT2232H

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jaymind
Contributor IV

Hello,

I used i.MX6Q and interfaced FTDI FT2232H in MPSSE mode on custom board, running it at 30MHz clock rate and Latency Timer is 255,

My FTDI FT2232H chip talk with ALTERA FPGA using SPI protocol.

I have downloaded libraries from below link and compiled with my App. code:

http://www.ftdichip.com/Support/SoftwareExamples/MPSSE/LibMPSSE-SPI/LibMPSSE-SPI_source.zip

I observe that the output signals show Read and Write transactions taking almost 3ms instead of few micro seconds.

On the code side the Read transactions take maximum 500us.

So, Is there any setting inside FTDI chip to decrease these timing delays or Do I need to choose another drivers ?

Regards

Jaymin D

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854 次查看
igorpadykov
NXP Employee
NXP Employee

Hi Jaymin

suggest to post this to ftdi support

FTDI Support

Best regards

igor

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jaymind
Contributor IV

OK.

Thanks...

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