Read access to OCRAM from M4 core

[sameer11]

Hi,
I am testing one setup that has two executables, one running on A53 core and other running on M4 core. I am using Messaging Unit peripheral for establishing communication between cores. First binary from A53 writes the data (String data) at every one second interval and generates an interrupt at processor B side and I am trying to read OCRAM free area location 0x00910000 from M4 as soon as ISR is invoked on processor B. 
But as soon as I perform first read access, the pointer that is pointing to OCRAM is not updating with new data.
e.g "String1" at t1 second
      "String2" at t2 second
      "String3" at t3 second.
If I try to read from t2 time interval then pointer gets updated only once with String2 and never gets updated with new data.
But If I try it the other way round i.e writing strings from M4 to OCRAM same location at every one second and performing consecutive read from A53 then I am not facing any issue in receiving the updated data strings. On A53 side, I am using the same reading mechanism using pointer. Is there any limitation from M4 core to perform consecutive read while A53 is accessing the memory. 
I am printing the strings on serial terminal.

Regards,
Sameer

[sameer11]

Hi Igor, 

Thanks for the references. I am using var-som-mx8m mini board and have built one baremetal application on M4. We are not using rpmsg for this and kept the scope of implementation very limited as we just need to demonstrate simple read/write mechanism between cores using shared memory. 

One update is that when I try to read and write OCRAM using only M4 binary I am able to do that by generating MUA interrupt from M4 itself and then copying the data using ISR.

/*Code running on M4*/

MU_M4_ISR{

disableInterrupt();
readflag = true; //
MUB->BSR |= (uint32_t)((1 << GIP0)); //Clear General Interrupt no. 1 (30th bit)
count++; //increment counter to track ISR count
//readTestDatafromMem();
enableInterrupt();

}

/*Send Function*/

{

memcpy(&mem_ptr_a53->shared_buffer[0], &string1, 16);   //copy data to OCRAM 0x00910000
MUA->ACR |= (uint32_t) ((1 << 18));  //Generate gen. intr 0

}

But when I do the same using A53 binary that sends data and generates intr. I am able to read just once from OCRAM same memory location using M4 binary. M4 is receiving proper interrupts from A53 but data from OCRAM is copied only once. It seems like when A53 maps the OCRAM memory it locks or limits M4 read access to OCRAM's same memory location to just once.

Thanks 

Sameer

[igorpadykov]

Hi Sameer

what board and software used in the case. May be recommended to test on NXP EVK reference board

with latest Linux 5.10.35_2.0.0 and M4 MCUXpressso SDK from  https://mcuxpresso.nxp.com/en/welcome

https://www.nxp.com/design/software/embedded-software/i-mx-software/embedded-linux-for-i-mx-applicat...

Examples of communication between two cores can be found in

AN12195  Implement Low-Power Audio on i.MX8M

AN12195SW

AN13201  i.MX 8M Mini Heterogenous Low Power Voice Control Solution

https://www.nxp.com/docs/en/application-note/AN13201.pdf

Best regards
igor

[sameer11]

Hi,

Issue is resolved, there was bus cache related issue which was not allowing to read the address of the shared memory OCRAM more than once.

Thanks for the support!

Regards,

Sameer