Hi Igor,
Thanks for the references. I am using var-som-mx8m mini board and have built one baremetal application on M4. We are not using rpmsg for this and kept the scope of implementation very limited as we just need to demonstrate simple read/write mechanism between cores using shared memory.
One update is that when I try to read and write OCRAM using only M4 binary I am able to do that by generating MUA interrupt from M4 itself and then copying the data using ISR.
/*Code running on M4*/
MU_M4_ISR{
disableInterrupt();
readflag = true; //
MUB->BSR |= (uint32_t)((1 << GIP0)); //Clear General Interrupt no. 1 (30th bit)
count++; //increment counter to track ISR count
//readTestDatafromMem();
enableInterrupt();
}
/*Send Function*/
{
memcpy(&mem_ptr_a53->shared_buffer[0], &string1, 16); //copy data to OCRAM 0x00910000
MUA->ACR |= (uint32_t) ((1 << 18)); //Generate gen. intr 0
}
But when I do the same using A53 binary that sends data and generates intr. I am able to read just once from OCRAM same memory location using M4 binary. M4 is receiving proper interrupts from A53 but data from OCRAM is copied only once. It seems like when A53 maps the OCRAM memory it locks or limits M4 read access to OCRAM's same memory location to just once.
Thanks
Sameer
