Hello,
Please check PCIe clock configuration.
HW Design Checking List for i.Mx6DQSDL Rev2.9 contains useful recommendations
about using (external) PCIe clock :
"Due to CLKx_P/N is LVDS port and don't match with PCIe reference clock specification.
For PCIe Gen1 application, following low cost solution can be used(DC bias and AC
impedance should be considered). Please refer to "HW Design Checking List for i.Mx6DQSDL
Rev2.7.xlsx", sheet "Schematic", Ref12 for more info."
"PCIe reference clock solution which provided by CLKx_N/P of i.MX6 chip can't pass PCIe
Gen2 compliance test. Recommend using external PCIe 2.0/3.0 clock generator with 2 HCSL
outputs solution. One clock channel connect to i.MX6 as a reference input, please click
Ref14 ("HW Design Checking List for i.Mx6DQSDL Rev2.9.xlsx") for reference circuit.
Another clock channel should connect to PCIe connector, please contact generator vendor
for detailed design guide."
HW Design Checking List for i.MX6DQSDL
Have a great day,
Yuri
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